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1. 发明授权

US08722519B2 Integrated assist features for epitaxial growth 有权
标题翻译：用于外延生长的集成辅助功能
公开(公告)号：US08722519B2
公开(公告)日：2014-05-13
申请号：US13182568
申请日：2011-07-14
申请人： Omar Zia , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L27/07
CPC分类号： H01L21/02595 , H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

2. 发明申请

US20080217714A1 SEMICONDUCTOR DEVICE HAVING TILES FOR DUAL-TRENCH INTEGRATION AND METHOD THEREFOR 有权
标题翻译：具有双路整合的电路的半导体器件及其方法
公开(公告)号：US20080217714A1
公开(公告)日：2008-09-11
申请号：US11683236
申请日：2007-03-07
申请人： Omar Zia , Ruiqi Tian
发明人： Omar Zia , Ruiqi Tian
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/8249 , H01L21/84
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.
摘要翻译：一种形成半导体器件的方法包括提供具有第一区域和第二区域的半导体衬底。第一区域具有一个或多个第一元件，而第二区域具有一个或多个第二元件。第一个元素与第二个元素不同。定义了半导体器件上的瓦片特征的瓦片位置和第一瓦片表面区域。半导体衬底的第一区域和第二区域都形成有源半导体层。使用负色调掩模在瓷砖位置的有源半导体层中形成第一沟槽。第一沟槽具有第一深度并且形成瓷砖特征的至少一部分。使用正色调掩模在有源半导体层中形成第二沟槽。第二沟槽具有与第一深度不同的第二深度。

3. 发明授权

US07785983B2 Semiconductor device having tiles for dual-trench integration and method therefor 有权
标题翻译：具有用于双沟槽集成的瓦片的半导体器件及其方法
公开(公告)号：US07785983B2
公开(公告)日：2010-08-31
申请号：US11683236
申请日：2007-03-07
申请人： Omar Zia , Ruiqi Tian
发明人： Omar Zia , Ruiqi Tian
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/8249 , H01L21/84
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.
摘要翻译：一种形成半导体器件的方法包括提供具有第一区域和第二区域的半导体衬底。第一区域具有一个或多个第一元件，而第二区域具有一个或多个第二元件。第一个元素与第二个元素不同。定义了半导体器件上的瓦片特征的瓦片位置和第一瓦片表面区域。半导体衬底的第一区域和第二区域都形成有源半导体层。使用负色调掩模在瓷砖位置的有源半导体层中形成第一沟槽。第一沟槽具有第一深度并且形成瓷砖特征的至少一部分。使用正色调掩模在有源半导体层中形成第二沟槽。第二沟槽具有与第一深度不同的第二深度。

4. 发明申请

US20110269300A1 Integrated Assist Features for Epitaxial Growth 有权
标题翻译：外延生长的综合辅助特征
公开(公告)号：US20110269300A1
公开(公告)日：2011-11-03
申请号：US13182568
申请日：2011-07-14
申请人： Omar Zia , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/20 , G06F17/50
CPC分类号： H01L21/02595 , H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

5. 发明授权

US08003539B2 Integrated assist features for epitaxial growth 有权
标题翻译：用于外延生长的集成辅助功能
公开(公告)号：US08003539B2
公开(公告)日：2011-08-23
申请号：US11650253
申请日：2007-01-04
申请人： Omar Zia , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/311
CPC分类号： H01L21/02595 , H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

6. 发明授权

US07470624B2 Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation 有权
标题翻译：用于补偿的外延生长体/ SOI混合瓦的综合辅助功能
公开(公告)号：US07470624B2
公开(公告)日：2008-12-30
申请号：US11651253
申请日：2007-01-08
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/302
CPC分类号： H01L21/84 , G06F2217/12 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823481 , H01L21/823878 , H01L27/1203 , H01L29/66651 , Y02P90/265
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301）（b）从第一数据集导出第一沟槽CMP掩模组（307）和至少一个外延生长掩模组（321,331），其中所述至少一个外延生长掩模组对应于存在的瓦片（305,307）在第一（203）和第二（207）不同的半导体表面上; （c）重新配置第一沟槽CMP掩模组以考虑至少一个外延生长掩模组，由此限定第二沟槽CMP掩模组（308），其中第二沟槽CMP掩模组限定一组沟槽CMP瓦片; 和（d）使用第二沟槽CMP掩模组来制造半导体器件。

7. 发明申请

US20080168417A1 Integrated assist features for epitaxial growth bulk tiles with compensation 有权
标题翻译：具有补偿的外延生长块体的综合辅助功能
公开(公告)号：US20080168417A1
公开(公告)日：2008-07-10
申请号：US11650254
申请日：2007-01-04
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： H01L29/045 , G06F2217/12 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/31053 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/66651 , Y02P90/265
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301）（b）从第一数据组导出第一沟槽CMP掩模集（307）和第一外延生长掩模组（309），其中通过去除子集（305）从第一数据集导出第一外延生长掩模集合，由所述第一数据集定义并且将所述瓦片的子集合合到所述第一外延生长掩模集合中的所述瓦片; 以及（c）重新配置第一沟槽CMP掩模集合以考虑第一外延生长掩模集合，从而限定第二沟槽CMP掩模集合（308）。

8. 发明申请

US20080168418A1 Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation 有权
标题翻译：用于补偿的外延生长体/ SOI混合瓦的综合辅助功能
公开(公告)号：US20080168418A1
公开(公告)日：2008-07-10
申请号：US11651253
申请日：2007-01-08
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： H01L21/84 , G06F2217/12 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823481 , H01L21/823878 , H01L27/1203 , H01L29/66651 , Y02P90/265
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301）（b）从第一数据集导出第一沟槽CMP掩模组（307）和至少一个外延生长掩模组（321,331），其中所述至少一个外延生长掩模组对应于存在的瓦片（305,307）在第一（203）和第二（207）不同的半导体表面上; （c）重新配置第一沟槽CMP掩模组以考虑至少一个外延生长掩模组，由此限定第二沟槽CMP掩模组（308），其中第二沟槽CMP掩模组限定一组沟槽CMP瓦片; 和（d）使用第二沟槽CMP掩模组来制造半导体器件。

9. 发明申请

US20080164559A1 Integrated assist features for epitaxial growth 有权
标题翻译：用于外延生长的集成辅助功能
公开(公告)号：US20080164559A1
公开(公告)日：2008-07-10
申请号：US11650253
申请日：2007-01-04
申请人： Omar Zia , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/763 , H01L29/02
CPC分类号： H01L21/02595 , H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

10. 发明授权

US08741743B2 Integrated assist features for epitaxial growth 有权
标题翻译：用于外延生长的集成辅助功能
公开(公告)号：US08741743B2
公开(公告)日：2014-06-03
申请号：US11650697
申请日：2007-01-05
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/7624 , H01L21/76224 , H01L21/76229 , H01L21/76278 , H01L21/76283
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）产生用于半导体器件中特征的外延生长的第一掩模，所述第一掩模限定一组外延片（219）; （b）产生用于限定所述半导体器件的有源区的第二掩模，所述第二掩模限定一组有源瓦片（229）; 和（c）使用第一和第二掩模来制造半导体器件。

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