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1. 发明申请

US20130248985A1 METHODS OF FORMING REPLACEMENT GATE STRUCTURES WITH A RECESSED CHANNEL 有权
标题翻译：形成更换通道结构的方法
公开(公告)号：US20130248985A1
公开(公告)日：2013-09-26
申请号：US13429787
申请日：2012-03-26
申请人： Kuldeep Amarnath , Michael Hargrove , Srikanth Samavedam
发明人： Kuldeep Amarnath , Michael Hargrove , Srikanth Samavedam
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1033 , H01L29/0847 , H01L29/42376 , H01L29/66545 , H01L29/66553 , H01L29/66621 , H01L29/66636 , H01L29/7848
摘要： Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.
摘要翻译：本文公开了形成具有凹陷沟道区域的替换栅极结构的各种方法。在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，去除牺牲栅极结构，从而限定具有侧壁的初始栅极开口并暴露衬底的表面，并在衬底的暴露表面上执行蚀刻工艺衬底以在衬底中限定凹陷通道。该方法包括在初始栅极开口的侧壁上的初始栅极开口内形成侧壁间隔物以由此限定最终栅极开口并在最终栅极开口中形成替换栅极结构的附加步骤。

2. 发明申请

US20070077698A1 METHOD FOR FABRICATING DUAL-METAL GATE DEVICE 有权
标题翻译：用于制造双金属栅极装置的方法
公开(公告)号：US20070077698A1
公开(公告)日：2007-04-05
申请号：US11530058
申请日：2006-09-08
申请人： David Gilmer , Srikanth Samavedam , Philip Tobin
发明人： David Gilmer , Srikanth Samavedam , Philip Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。在半导体衬底上沉积诸如HfO 2 N的栅极电介质（34）。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

3. 发明申请

US20050150535A1 Method for forming a thin-film thermoelectric device including a phonon-blocking thermal conductor 审中-公开
标题翻译：用于形成包括声阻挡热导体的薄膜热电装置的方法
公开(公告)号：US20050150535A1
公开(公告)日：2005-07-14
申请号：US11020836
申请日：2004-12-23
申请人： Srikanth Samavedam , Uttam Ghoshal , Tat Ngai
发明人： Srikanth Samavedam , Uttam Ghoshal , Tat Ngai
IPC分类号： H01L23/38 , H01L35/12 , H01L35/30 , H01L35/34 , H01L37/00
CPC分类号： H01L23/38 , H01L35/30 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A vertical, monolithic, thin-film thermoelectric device is described. Thermoelectric elements of opposing conductivity types may be coupled electrically in series and thermally in parallel by associated electrodes on a single substrate, reducing the need for mechanisms to attach multiple substrates or components. Phonon transport may be separated from electron transport in a thermoelectric element. A thermoelectric element may have a thickness less than an associated thermalization length. An insulating film between an electrode having a first temperature and an electrode having a second temperature may be a low-thermal conductivity material, a low-k, or ultra-low-k dielectric. Phonon thermal conductivity between a thermoelectric element and an electrode may be reduced without a significant reduction in electron thermal conductivity, as compared to other thermoelectric devices. A phonon conduction impeding material may be included in regions coupling an electrode to an associated thermoelectric element (e.g., a liquid metal).
摘要翻译：描述了垂直的，整体的薄膜热电装置。相反导电类型的热电元件可以在单个衬底上由相关联的电极串联电耦合并且热并联，从而减少了附接多个衬底或部件的机构的需要。声子传输可以与热电元件中的电子传输分离。热电元件可以具有小于相关联的热化长度的厚度。具有第一温度的电极和具有第二温度的电极之间的绝缘膜可以是低热导率材料，低k或超低k电介质。与其他热电装置相比，热电元件和电极之间的声子热导率可以减小而电子热导率显着降低。声导电阻碍材料可以包括在将电极耦合到相关联的热电元件（例如，液态金属）的区域中。

4. 发明授权

US09099492B2 Methods of forming replacement gate structures with a recessed channel 有权
标题翻译：用凹槽形成替换栅极结构的方法
公开(公告)号：US09099492B2
公开(公告)日：2015-08-04
申请号：US13429787
申请日：2012-03-26
申请人： Kuldeep Amarnath , Michael Hargrove , Srikanth Samavedam
发明人： Kuldeep Amarnath , Michael Hargrove , Srikanth Samavedam
IPC分类号： H01L29/66 , H01L21/336 , H01L29/78
CPC分类号： H01L29/1033 , H01L29/0847 , H01L29/42376 , H01L29/66545 , H01L29/66553 , H01L29/66621 , H01L29/66636 , H01L29/7848
摘要： Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.
摘要翻译：本文公开了形成具有凹陷沟道区域的替换栅极结构的各种方法。在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，去除牺牲栅极结构，从而限定具有侧壁的初始栅极开口并暴露衬底的表面，并在衬底的暴露表面上执行蚀刻工艺衬底以在衬底中限定凹陷通道。该方法包括在初始栅极开口的侧壁上的初始栅极开口内形成侧壁间隔物以由此限定最终栅极开口并在最终栅极开口中形成替换栅极结构的附加步骤。

5. 发明申请

US20050282326A1 Method for fabricating dual-metal gate device 审中-公开
标题翻译：双金属栅极器件制造方法
公开(公告)号：US20050282326A1
公开(公告)日：2005-12-22
申请号：US11211798
申请日：2005-08-25
申请人： David Gilmer , Srikanth Samavedam , Philip Tobin
发明人： David Gilmer , Srikanth Samavedam , Philip Tobin
IPC分类号： H01L21/8238 , H01L21/338
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。在半导体衬底上沉积诸如HfO 2 N的栅极电介质（34）。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

6. 发明申请

US20050095763A1 Method of forming an NMOS transistor and structure thereof 审中-公开
标题翻译：形成NMOS晶体管的方法及其结构
公开(公告)号：US20050095763A1
公开(公告)日：2005-05-05
申请号：US10696346
申请日：2003-10-29
申请人： Srikanth Samavedam , James Schaeffer , Philip Tobin , Bikas Maiti , Joseph Mogab
发明人： Srikanth Samavedam , James Schaeffer , Philip Tobin , Bikas Maiti , Joseph Mogab
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L29/78 , H01L21/4763 , H01L21/8234
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/823842 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： In one embodiment, metal boride (MBx), metal carbide (MCx), metal carbo-nitrides (MCxNy), metal boro-carbide (MBxCy), metal boro-nitride (MBxNy) or metal boro-carbo-nitride (MBxCyNz), wherein the metal is a transition metal (Group III-XII of the periodic chart) may be suitable as NMOS gate electrode materials. Such materials, such as TaC and LaB6, can be formed to have work functions that are within approximately 4-4.3 eV, which is desirable for NMOS transistors. In addition, the amount of carbon or nitrogen can be adjusting the amount of carbon or nitrogen in the precursor to achieve a predetermined metal work function.
摘要翻译：在一个实施方案中，金属硼化物（MB xS x），金属碳化物（MC xS），金属碳氮化物（MC x N x N）金属硼化物（MB x x C y），金属硼氮化物（MB x N x N）或金属硼 - 碳氮化物（金属氧化物），其中金属是过渡金属（周期图的III-XII族）可以适合作为NMOS栅电极材料。这种材料，例如TaC和LaB 6，可以形成为具有大约4-4.3eV的功函数，这对NMOS晶体管是期望的。此外，碳或氮的量可以调节前体中的碳或氮的量以实现预定的金属功能。

7. 发明申请

US20130224945A1 METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS 有权
标题翻译：形成具有更换盖的块状FINFET器件的方法，以减少通过泄漏电流的冲击
公开(公告)号：US20130224945A1
公开(公告)日：2013-08-29
申请号：US13408139
申请日：2012-02-29
申请人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans Van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
发明人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans Van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L29/66795
摘要： One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷，以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

8. 发明授权

US09099525B2 Blanket EPI super steep retrograde well formation without Si recess 有权
标题翻译：毯子EPI超陡逆行井形成无Si凹陷
公开(公告)号：US09099525B2
公开(公告)日：2015-08-04
申请号：US13729207
申请日：2012-12-28
申请人： Laegu Kang , Vara Govindeswara Reddy Vakada , Michael P. Ganz , Yi Qi , Puneet Khanna , Sri Charan Vemula , Srikanth Samavedam
发明人： Laegu Kang , Vara Govindeswara Reddy Vakada , Michael P. Ganz , Yi Qi , Puneet Khanna , Sri Charan Vemula , Srikanth Samavedam
IPC分类号： H01L21/762 , H01L29/66 , H01L29/10 , H01L21/8238 , H01L29/165
CPC分类号： H01L29/0692 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/165 , H01L29/167 , H01L29/66651
摘要： A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
摘要翻译：提供了在场氧化物和外延生长的硅之间形成具有受控步长的SSRW FET的方法以及所得到的器件。实施例包括在衬底上提供SiN层，通过SiN层形成第一，第二和第三间隔的场区氧化物的STI区域并进入衬底，通过受控的消光去除每个STI区域的场氧化物的顶部部分，去除 SiN层，在第一和第二STI区域之间的衬底中形成n型区域和在第二和第三STI区域之间的衬底中的p型区域，并且在衬底上在n上外延生长Si基层型和p型区。

9. 发明授权

US08809178B2 Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents 有权
标题翻译：用替换栅极形成大量FinFET器件的方法，以减少冲击穿过漏电流
公开(公告)号：US08809178B2
公开(公告)日：2014-08-19
申请号：US13408139
申请日：2012-02-29
申请人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
发明人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L29/66795
摘要： One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷，以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

10. 发明申请

US20140183638A1 METHODS OF USING A TRENCH SALICIDE ROUTING LAYER 有权
标题翻译：使用TRENCH SALICIDE ROUTING LAYER的方法
公开(公告)号：US20140183638A1
公开(公告)日：2014-07-03
申请号：US13729843
申请日：2012-12-28
申请人： Mahbub RASHED , Srikanth Samavedam , David Doman , Navneet Jain , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub RASHED , Srikanth Samavedam , David Doman , Navneet Jain , Subramani Kengeri , Suresh Venkatesan
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L21/845 , H01L21/823821 , H01L27/0924 , H01L27/1211
摘要： Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.
摘要翻译：公开了使用分段沟槽自对准硅层选择性地连接翅片结构的方法，以及所得到的装置。实施例包括：在衬底上提供至少一个栅极结构; 在与所述至少一个栅极结构相交的垂直方向上提供第一和第二鳍结构; 以及提供自对准层的第一段，所述第一段沿着水平方向形成并且与所述第二鳍结构连接并与所述第一鳍结构分离。

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