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1. 发明授权

US06841448B2 Method for fabricating embedded nonvolatile semiconductor memory cells 有权
标题翻译：嵌入式非易失性半导体存储单元的制造方法
公开(公告)号：US06841448B2
公开(公告)日：2005-01-11
申请号：US10045278
申请日：2002-01-14
申请人： Oliver Gehring , Wolfram Langheinrich
发明人： Oliver Gehring , Wolfram Langheinrich
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/105 , H01L21/8239 , H01L21/321
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/105 , H01L27/11573 , Y10S438/981
摘要： A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having a high-voltage region, a memory region and a logic region. The first insulating layer is removed in the memory region, and a second insulating layer is formed. A charge-storing layer is formed and patterned along with a third insulating layer. The first to third insulating layers and also the charge-storing layer are removed in the logic region. A fourth insulating layer is formed and a conductive control layer is formed and patterned.
摘要翻译：描述了一种用于制造嵌入式非易失性半导体存储单元的方法。该方法包括在具有高电压区域，存储区域和逻辑区域的衬底上形成第一绝缘层。在存储区域中去除第一绝缘层，形成第二绝缘层。电荷存储层与第三绝缘层一起形成并图案化。在逻辑区域中去除第一至第三绝缘层和电荷存储层。形成第四绝缘层，形成导电控制层并构图。

2. 发明授权

US06940121B2 Semiconductor memory cell 失效
标题翻译：半导体存储单元
公开(公告)号：US06940121B2
公开(公告)日：2005-09-06
申请号：US10399929
申请日：2001-09-19
申请人： Oliver Gehring
发明人： Oliver Gehring
IPC分类号： H01L29/423 , H01L29/788
CPC分类号： H01L29/42336 , H01L29/7881
摘要： A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region; a control gate electrode surrounding the trench; and a second insulation layer on the surface of the semiconductor substrate. The semiconductor memory cell further includes a conductive layer positioned on the second insulation layer. The conductive layer includes a channel region positioned above the floating gate electrode. The semiconductor memory cell also includes a source region and a drain region. The source region and the drain region are each formed in the conductive layer. The source region and the drain region are also connected to the channel region.
摘要翻译：半导体存储单元包括限定具有沟槽壁的沟槽的半导体衬底。所述半导体存储单元还包括位于所述沟槽内的浮置栅电极，并通过第一绝缘区域与所述沟槽壁绝缘; 围绕所述沟槽的控制栅电极; 以及在半导体衬底的表面上的第二绝缘层。半导体存储单元还包括位于第二绝缘层上的导电层。导电层包括位于浮栅电极上方的沟道区。半导体存储单元还包括源极区和漏极区。源极区域和漏极区域各自形成在导电层中。源极区域和漏极区域也连接到沟道区域。

3. 发明授权

US06459296B2 Method, system and method of using a component for setting the electrical characteristics of microelectronic circuit configurations 有权
标题翻译：使用组件设置微电子电路配置的电气特性的方法，系统和方法
公开(公告)号：US06459296B2
公开(公告)日：2002-10-01
申请号：US09916668
申请日：2001-07-26
申请人： Stephan Bradl , Oliver Gehring , Olaf Heitzsch
发明人： Stephan Bradl , Oliver Gehring , Olaf Heitzsch
IPC分类号： H03K19177
CPC分类号： G11C27/005
摘要： The electrical characteristic of a microelectronic circuit configuration that has at least one analog electronic unit is set. In a configuration step, by feeding and/or extracting electrical charge, the analog electronic unit is put into a state which permanently determines the analog electrical characteristics of the unit. In particular, the floating gate of an EEPROM cell is charged up to a freely selectable charge value lying within a continuous range.
摘要翻译：设置具有至少一个模拟电子单元的微电子电路配置的电气特性。在配置步骤中，通过馈送和/或提取电荷，模拟电子单元处于永久确定单元的模拟电气特性的状态。特别地，EEPROM单元的浮置栅极被充电至可连续范围内的可自由选择的电荷值。

4. 发明授权

US06403473B1 Process for producing metal-containing layers 有权
标题翻译：含金属层的制造方法
公开(公告)号：US06403473B1
公开(公告)日：2002-06-11
申请号：US09315329
申请日：1999-05-20
申请人： Sven Schmidbauer , Alexander Ruf , Oliver Gehring
发明人： Sven Schmidbauer , Alexander Ruf , Oliver Gehring
IPC分类号： H01L2144
CPC分类号： C23C14/586 , C23C14/165 , C23C14/58 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76856
摘要： A process for producing metal-containing layers, in particular metal-containing diffusion barriers, contact layers and/or antireflection layers. The process according to the invention has a first step in which a metal layer having a predetermined thickness at an elevated temperature is applied to a semiconductor structure. Next, the metal layer is cooled in a nitrogen-containing atmosphere, resulting in a metal nitride layer being formed.
摘要翻译：一种生产含金属层，特别是含金属的扩散阻挡层，接触层和/或抗反射层的方法。根据本发明的方法具有第一步骤，其中在升高的温度下具有预定厚度的金属层被施加到半导体结构。接着，将金属层在含氮气氛中冷却，形成金属氮化物层。

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