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1. 发明申请

US20100232202A1 DUAL PORT MEMORY DEVICE 有权
标题翻译：双端口存储器件
公开(公告)号：US20100232202A1
公开(公告)日：2010-09-16
申请号：US12404892
申请日：2009-03-16
申请人： Olga R. Lu , Lawrence F. Childs , Thomas W. Liston
发明人： Olga R. Lu , Lawrence F. Childs , Thomas W. Liston
IPC分类号： G11C5/06 , G11C8/16 , G11C8/00
CPC分类号： G11C8/16 , G11C8/10 , G11C11/412 , G11C11/413 , G11C11/419
摘要： A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.
摘要翻译：一种具有存储节点，预充电节点，第一，第二，第三和第四晶体管以及控制模块的多端口存储器件。第一晶体管包括连接到存储节点的电流电极，连接到第一位线的另一电流电极和连接到第一字线的栅极。第二晶体管包括连接到存储节点的电流电极，连接到第二位线的另一个电流电极和连接到第二字线的栅极。第三晶体管包括连接到参考节点的电流电极，连接到第一位线的另一电流电极和栅极。第四晶体管包括连接到预充电节点的电流电极，连接到第二位线的另一电流电极和栅极。响应于在第二晶体管处的第一存储模块的虚拟访问，控制模块停用第四晶体管。

2. 发明授权

US07940599B2 Dual port memory device 有权
标题翻译：双端口存储设备
公开(公告)号：US07940599B2
公开(公告)日：2011-05-10
申请号：US12404892
申请日：2009-03-16
申请人： Olga R. Lu , Lawrence F. Childs , Thomas W. Liston
发明人： Olga R. Lu , Lawrence F. Childs , Thomas W. Liston
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C8/16 , G11C8/10 , G11C11/412 , G11C11/413 , G11C11/419
摘要： A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.
摘要翻译：一种具有存储节点，预充电节点，第一，第二，第三和第四晶体管以及控制模块的多端口存储器件。第一晶体管包括连接到存储节点的电流电极，连接到第一位线的另一电流电极和连接到第一字线的栅极。第二晶体管包括连接到存储节点的电流电极，连接到第二位线的另一个电流电极和连接到第二字线的栅极。第三晶体管包括连接到参考节点的电流电极，连接到第一位线的另一电流电极和栅极。第四晶体管包括连接到预充电节点的电流电极，连接到第二位线的另一电流电极和栅极。响应于在第二晶体管处的第一存储模块的虚拟访问，控制模块停用第四晶体管。

3. 发明申请

US20080205176A1 MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL 有权
标题翻译：具有时序控制功能的内存
公开(公告)号：US20080205176A1
公开(公告)日：2008-08-28
申请号：US11677808
申请日：2007-02-22
申请人： Mark W. Jetton , Lawrence F. Childs , Olga R. Lu , Glenn E. Starnes
发明人： Mark W. Jetton , Lawrence F. Childs , Olga R. Lu , Glenn E. Starnes
IPC分类号： G11C7/06 , G11C7/14
CPC分类号： G11C7/22 , G11C7/227
摘要： A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.
摘要翻译：一种具有至少一个存储器阵列块的存储器，提供了包括N个字线的至少一个存储器阵列块，其中N大于1。存储器包括耦合到至少一个存储器阵列块的多个读出放大器。所述存储器还包括至少一个伪位线，其中所述至少一个伪位线包括M个伪位单元，其中M等于N。所述存储器还包括耦合到所述至少一个虚拟位线的定时电路，其中所述定时电路包括耦合到感测电路的至少一叠下拉晶体管，用于产生用于存储器存取定时控制的锁存控制输出信号。定时控制可以包括产生感测触发信号以使多个读出放大器能够进行读取操作和/或产生用于终止存储器访问的本地复位信号，例如禁用多个写入驱动器进行写入操作。

4. 发明授权

US07800959B2 Memory having self-timed bit line boost circuit and method therefor 有权
标题翻译：具有自定时位线升压电路的存储器及其方法
公开(公告)号：US07800959B2
公开(公告)日：2010-09-21
申请号：US12233922
申请日：2008-09-19
申请人： Lawrence F. Childs , Craig D. Gunderson , Olga R. Lu , James D. Burnett
发明人： Lawrence F. Childs , Craig D. Gunderson , Olga R. Lu , James D. Burnett
IPC分类号： G11C16/00
CPC分类号： G11C7/1048 , G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/41 , G11C11/419 , G11C29/12 , G11C29/12005 , G11C2029/1204
摘要： A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.
摘要翻译：存储器具有存储器单元阵列，列逻辑，写驱动器，电压检测器和自举电路。存储器单元的阵列耦合到位线对和字线对。列逻辑耦合到阵列，并用于将选定的一对位线耦合到一对数据线。写驱动器耦合到该对数据线。当写入驱动器在一对数据线的写入期间，当一对数据线的第一数据线的电压下降到低于第一电平时，电压检测器提供启动升压信号。自举电路响应于升压使能信号而降低第一数据线的电压。当编译器中的位线上的存储单元数量可能显着变化时，这是特别有益的。

5. 发明授权

US07746716B2 Memory having a dummy bitline for timing control 有权
标题翻译：具有用于定时控制的虚拟位线的存储器
公开(公告)号：US07746716B2
公开(公告)日：2010-06-29
申请号：US11677808
申请日：2007-02-22
申请人： Mark W. Jetton , Lawrence F. Childs , Olga R. Lu , Glenn E. Starnes
发明人： Mark W. Jetton , Lawrence F. Childs , Olga R. Lu , Glenn E. Starnes
IPC分类号： G11C7/00 , G11C7/02 , G11C8/00
CPC分类号： G11C7/22 , G11C7/227
摘要： A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.
摘要翻译：一种具有至少一个存储器阵列块的存储器，提供了包括N个字线的至少一个存储器阵列块，其中N大于1。存储器包括耦合到至少一个存储器阵列块的多个读出放大器。所述存储器还包括至少一个伪位线，其中所述至少一个伪位线包括M个伪位单元，其中M等于N。所述存储器还包括耦合到所述至少一个虚拟位线的定时电路，其中所述定时电路包括耦合到感测电路的至少一叠下拉晶体管，用于产生用于存储器存取定时控制的锁存控制输出信号。定时控制可以包括产生感测触发信号以使多个读出放大器能够进行读取操作和/或产生用于终止存储器访问的本地复位信号，例如禁用多个写入驱动器进行写入操作。

6. 发明申请

US20100074032A1 MEMORY HAVING SELF-TIMED BIT LINE BOOST CIRCUIT AND METHOD THEREFOR 有权
标题翻译：具有自相位线升压电路的存储器及其方法
公开(公告)号：US20100074032A1
公开(公告)日：2010-03-25
申请号：US12233922
申请日：2008-09-19
申请人： Lawrence F. Childs , Craig D. Gunderson , Olga R. Lu , James D. Burnett
发明人： Lawrence F. Childs , Craig D. Gunderson , Olga R. Lu , James D. Burnett
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/41 , G11C11/419 , G11C29/12 , G11C29/12005 , G11C2029/1204
摘要： A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.
摘要翻译：存储器具有存储器单元阵列，列逻辑，写驱动器，电压检测器和自举电路。存储器单元的阵列耦合到位线对和字线对。列逻辑耦合到阵列，并用于将选定的一对位线耦合到一对数据线。写驱动器耦合到该对数据线。当写入驱动器在一对数据线的写入期间，当一对数据线的第一数据线的电压下降到低于第一电平时，电压检测器提供启动升压信号。自举电路响应于升压使能信号而降低第一数据线的电压。当编译器中的位线上的存储单元数量可能显着变化时，这是特别有益的。

7. 发明授权

US07292485B1 SRAM having variable power supply and method therefor 有权
标题翻译：具有可变电源的SRAM及其方法
公开(公告)号：US07292485B1
公开(公告)日：2007-11-06
申请号：US11461200
申请日：2006-07-31
申请人： Olga R. Lu , Lawrence F. Childs , Craig D. Gunderson
发明人： Olga R. Lu , Lawrence F. Childs , Craig D. Gunderson
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C11/413
摘要： A memory circuit has a memory array with a first line of memory cells, a second line of memory cells, a first power supply terminal, a first capacitance structure, a first power supply line coupled to the first line of memory cells; and a second power supply line coupled to the second line of memory cells. For the case where the second line of memory cells is selected for writing, a switching circuit couples the power supply terminal to the first power supply line, decouples the first power supply line from the second line of memory cells, and couples the second power supply line to the first capacitance structure. The result is a reduction in power supply voltage to the selected line of memory cells by charge sharing with the capacitance structure. This provides more margin in the write operation on a cell in the selected line of memory cells.
摘要翻译：存储器电路具有存储器阵列，其具有第一行存储器单元，第二行存储器单元，第一电源端子，第一电容结构，耦合到第一行存储器单元的第一电源线; 以及耦合到第二行存储器单元的第二电源线。对于第二行存储单元被选择用于写入的情况，开关电路将电源端子耦合到第一电源线，使第一电源线与第二行存储单元分离，并将第二电源线到第一个电容结构。结果是通过与电容结构的电荷共享来降低对选定的存储单元线的电源电压。这在存储器单元的所选行中的单元上的写入操作中提供了更多的余量。

8. 发明授权

US5440514A Write control for a memory using a delay locked loop 失效
标题翻译：使用延迟锁定环对内存进行写入控制
公开(公告)号：US5440514A
公开(公告)日：1995-08-08
申请号：US207510
申请日：1994-03-08
申请人： Stephen T. Flannagan , Ray Chang , Lawrence F. Childs
发明人： Stephen T. Flannagan , Ray Chang , Lawrence F. Childs
IPC分类号： G11C7/22 , G11C17/10
CPC分类号： G11C7/222 , G11C7/22
摘要： A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.
摘要翻译：存储器（20）包括用于控制存储器（20）的写周期的写控制延迟锁定环（52）。延迟锁定环（52）包括仲裁电路（264），电压控制延迟（VCD）电路（260）和VCD控制电路（265）。仲裁器电路（264）将时钟信号与来自VCD电路（260）的延迟的时钟信号进行比较。作为响应，仲裁器电路（264）向VCD控制电路（265）提供延迟信号。 VCD控制电路（265）接收延迟信号并调整延迟的时钟信号的传播延迟以补偿时钟频率的变化，以及补偿处理，温度和电源变化。

9. 发明授权

US5426381A Latching ECL to CMOS input buffer circuit 失效
标题翻译：将ECL锁存到CMOS输入缓冲电路
公开(公告)号：US5426381A
公开(公告)日：1995-06-20
申请号：US247819
申请日：1994-05-23
申请人： Stephen T. Flannagan , Lawrence F. Childs
发明人： Stephen T. Flannagan , Lawrence F. Childs
IPC分类号： H03K3/356 , H03K19/01
CPC分类号： H03K3/35606 , H03K3/356034 , H03K3/356113
摘要： A latching ECL to CMOS input buffer (20) has an input buffer (21) for receiving an ECL input signal, a CMOS latch (35), and driver circuits (55, 65). Transmission gates (31, 32) are used to couple the input buffer (21) to the latch (35) in response to a CMOS clock signal being a logic low. The driver circuits (55, 65) are coupled to transmission gates (31, 32). While the clock signal is a logic low, input nodes of the first and second driver circuits (55, 65) are precharged to a relatively high voltage in order to isolate the input signal from the first and second driver circuits (55, 65). The latch (35) both latches the logic state of the ECL input signal and converts the ECL input signal to CMOS logic levels. This allows an input signal to be latched and level converted within a relatively short period of time.
摘要翻译： CMOS输入缓冲器（20）的锁存ECL具有用于接收ECL输入信号的输入缓冲器（21），CMOS锁存器（35）和驱动器电路（55,65）。响应于CMOS时钟信号为逻辑低，传输门（31,32）用于将输入缓冲器（21）耦合到锁存器（35）。驱动电路（55,65）耦合到传输门（31,32）。当时钟信号为逻辑低电平时，第一和第二驱动电路（55,65）的输入节点被预充电到较高的电压，以隔离来自第一和第二驱动电路（55,65）的输入信号。锁存器（35）都锁存ECL输入信号的逻辑状态，并将ECL输入信号转换为CMOS逻辑电平。这允许输入信号在相对短的时间段内被锁存和电平转换。

10. 发明授权

US5400274A Memory having looped global data lines for propagation delay matching 失效
标题翻译：具有循环全局数据线以用于传播延迟匹配的存储器
公开(公告)号：US5400274A
公开(公告)日：1995-03-21
申请号：US236845
申请日：1994-05-02
申请人： Kenneth W. Jones , Lawrence F. Childs
发明人： Kenneth W. Jones , Lawrence F. Childs
IPC分类号： G11C7/10 , G11C5/06
CPC分类号： G11C7/10
摘要： A synchronous memory (50) having a looped global data line (80) reduces a difference between minimum and maximum propagation delays between different locations in a memory array (51) during a read cycle of the memory (50). The looped global data line (80) has a first portion (80') and a second portion (80"). The first portion (80') extends along an edge of the memory array (51) in a direction substantially parallel to a direction of the word lines of the array (51). Sense amplifiers (73-78) are coupled to the first portion (80') of the looped global data line (80). At one end of the array (51), the second portion (80") of the looped global data line extends back in an opposite direction to the first portion (80') and is coupled to output data circuits (84). Reducing the difference in propagation delays improves noise margins and allows increased operating speed.
摘要翻译：具有循环全局数据线（80）的同步存储器（50）在存储器（50）的读取周期期间减少存储器阵列（51）中的不同位置之间的最小和最大传播延迟之间的差异。环路全局数据线（80）具有第一部分（80'）和第二部分（80“）。第一部分（80'）沿着与阵列（51）的字线的方向基本平行的方向沿着存储器阵列（51）的边缘延伸。感测放大器（73-78）耦合到环路全局数据线（80）的第一部分（80'）。在阵列（51）的一端，环形全局数据线的第二部分（80“）在与第一部分（80'）相反的方向上延伸并耦合到输出数据电路（84）。降低传播延迟的差异可以提高噪音容限，并提高运行速度。

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