专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08286043B2 System, computer program product and method for testing a logic circuit 有权
标题翻译：用于测试逻辑电路的系统，计算机程序产品和方法
公开(公告)号：US08286043B2
公开(公告)日：2012-10-09
申请号：US12527347
申请日：2007-02-16
申请人： Oleksandr Sakada , Florian Bogenberger
发明人： Oleksandr Sakada , Florian Bogenberger
IPC分类号： G01R31/28 , G01R31/26 , G01R31/02
CPC分类号： G06F11/27 , G01R31/005 , G01R31/007 , G01R31/3183 , G01R31/3187
摘要： A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behavior, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine. At a test module output interface the overall test result may be outputted. The test routine includes instructions for outputting, by the part of the logic circuit, data to a test routine output interface which is not connected to the second test module input interface, for outputting information about the self-test result by the test routines without passing the information through the test module.
摘要翻译：一种用于测试具有两个或更多个测试例程模块的逻辑电路的系统。每个模块包含一组可由逻辑电路的（一部分）执行的指令。该组形成用于由逻辑电路的一部分进行自检的测试程序。自检包括对故障行为进行逻辑电路测试的部分，逻辑电路的一部分决定测试的自检结果。该系统包括测试模块，该测试模块可以通过使逻辑电路的一部分执行所选择的测试例程来执行通过对逻辑电路的至少一部分进行自检来使逻辑电路进行测试的测试应用，以及至少基于所执行的自我测试，由所述测试模块确定总体测试结果。测试模块包括用于激活所选择的测试例程的执行的控制输出接口。第二个测试模块输入接口可以从选定的测试程序中接收自检结果。在测试模块输出接口，可以输出整体测试结果。测试例程包括用逻辑电路的一部分将数据输出到未连接到第二测试模块输入接口的测试程序输出接口，用于通过测试例程输出关于自检结果的信息而不经过通过测试模块的信息。

2. 发明授权

US08793700B2 Synchronization of stateful elements in a processing resource using a scan chain 有权
标题翻译：使用扫描链来处理资源中的状态元素的同步
公开(公告)号：US08793700B2
公开(公告)日：2014-07-29
申请号：US12937891
申请日：2008-05-14
申请人： Florian Bogenberger , Anthony Reipold , Oleksandr Sakada
发明人： Florian Bogenberger , Anthony Reipold , Oleksandr Sakada
IPC分类号： G06F9/46 , G06F11/00
CPC分类号： G01R31/318594 , G06F11/1658
摘要： A processing resource apparatus comprises a reference processing module comprising a set of reference stateful elements and a target processing module comprising a set of target stateful elements. A scan chain having a first mode for supporting manufacture testing is also provided, the scan chain being arranged to couple the reference processing module to the target processing module. The scan chain also has a second mode capable of synchronizing the set of target stateful elements with the set of reference stateful elements in response to a synchronization signal.
摘要翻译：处理资源装置包括参考处理模块，该参考处理模块包括一组参考状态元素和包括一组目标状态元素的目标处理模块。还提供了具有用于支持制造测试的第一模式的扫描链，扫描链被布置成将参考处理模块耦合到目标处理模块。扫描链还具有能够响应于同步信号使目标状态元素集合与该组参考状态元素同步的第二模式。

3. 发明申请

US20110035750A1 PROCESSING RESOURCE APPARATUS AND METHOD OF SYNCHRONISING A PROCESSING RESOURCE 有权
标题翻译：加工资源设备和同步加工资源的方法
公开(公告)号：US20110035750A1
公开(公告)日：2011-02-10
申请号：US12937891
申请日：2008-05-14
申请人： Florian Bogenberger , Anthony Reipold , Oleksandr Sakada
发明人： Florian Bogenberger , Anthony Reipold , Oleksandr Sakada
IPC分类号： G06F9/46
CPC分类号： G01R31/318594 , G06F11/1658
摘要： A processing resource apparatus comprises a reference processing module comprising a set of reference stateful elements and a target processing module comprising a set of target stateful elements. A scan chain having a first mode for supporting manufacture testing is also provided, the scan chain being arranged to couple the reference processing module to the target processing module. The scan chain also has a second mode capable of synchronising the set of target stateful elements with the set of reference stateful elements in response to a synchronisation signal.
摘要翻译：处理资源装置包括参考处理模块，该参考处理模块包括一组参考状态元素和包括一组目标状态元素的目标处理模块。还提供了具有用于支持制造测试的第一模式的扫描链，扫描链被布置成将参考处理模块耦合到目标处理模块。扫描链还具有能够响应于同步信号使目标状态元素集合与该组参考状态元素同步的第二模式。

4. 发明申请

US20100107025A1 SYSTEM, COMPUTER PROGRAM PRODUCT AND METHOD FOR TESTING A LOGIC CIRCUIT 有权
标题翻译：系统，计算机程序产品和测试逻辑电路的方法
公开(公告)号：US20100107025A1
公开(公告)日：2010-04-29
申请号：US12527347
申请日：2007-02-16
申请人： Oleksandr Sakada , Florian Bogenberger
发明人： Oleksandr Sakada , Florian Bogenberger
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G01R31/005 , G01R31/007 , G01R31/3183 , G01R31/3187
摘要： A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behaviour, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine. At a test module output interface the overall test result may be outputted. The test routine includes instructions for outputting, by the part of the logic circuit, data to a test routine output interface which is not connected to the second test module input interface, for outputting information about the self-test result by the test routines without passing the information through the test module.
摘要翻译：一种用于测试具有两个或更多个测试例程模块的逻辑电路的系统。每个模块包含一组可由逻辑电路的（一部分）执行的指令。该组形成用于由逻辑电路的一部分进行自检的测试程序。自检包括对故障行为进行逻辑电路测试的部分，逻辑电路的一部分决定测试的自检结果。该系统包括测试模块，该测试模块可以通过使逻辑电路的一部分执行所选择的测试例程来执行通过对逻辑电路的至少一部分进行自检来使逻辑电路进行测试的测试应用，以及至少基于所执行的自我测试，由所述测试模块确定总体测试结果。测试模块包括用于激活所选择的测试例程的执行的控制输出接口。第二个测试模块输入接口可以从选定的测试程序中接收自检结果。在测试模块输出接口，可以输出整体测试结果。测试例程包括用逻辑电路的一部分将数据输出到未连接到第二测试模块输入接口的测试程序输出接口，用于通过测试例程输出关于自检结果的信息而不经过通过测试模块的信息。

5. 发明申请

US20110066779A1 DATA PROCESSING SYSTEM, DATA PROCESSING METHOD, AND APPARATUS 有权
标题翻译：数据处理系统，数据处理方法和装置
公开(公告)号：US20110066779A1
公开(公告)日：2011-03-17
申请号：US12599994
申请日：2007-05-25
申请人： Florian Bogenberger , Joachim Kruecken , Christopher Temple
发明人： Florian Bogenberger , Joachim Kruecken , Christopher Temple
IPC分类号： G06F13/40
CPC分类号： G06F11/1641 , G06F11/1487 , G06F11/1675 , G06F15/7842 , G06F2201/845
摘要： A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.
摘要翻译：数据处理系统可以包括第一数据路径和第二数据路径。一组组件可以包括系统组件和伙伴组件，每个组件具有用于传送数据的通信接口。组件可以相对于彼此以同步模式和非同步模式操作。该集合还可以包括连接到系统组件和伙伴组件的配置控制系统，用于将组控制为同步模式配置或非同步模式配置。配置控制系统可以包括将系统组件的通信接口连接到第一数据路径和第二数据路径的第一路径选择器模块和将伙伴组件的通信接口连接到第一数据路径的伙伴路径选择器模块，第二条数据路径。路径选择器模块可以被布置成使得根据配置能够经由从第一数据路径和第二数据路径选择的一个或多个所选择的数据路径将数据传送到相应的组件，并且通过未选择的方式禁止通信数据路径。

6. 发明申请

US20100213964A1 TIMER UNIT, SYSTEM, COMPUTER PROGRAM PRODUCT AND METHOD FOR TESTING A LOGIC CIRCUIT 有权
标题翻译：定时器单元，系统，计算机程序产品和测试逻辑电路的方法
公开(公告)号：US20100213964A1
公开(公告)日：2010-08-26
申请号：US12676699
申请日：2007-09-25
申请人： Florian Bogenberger , Leos Chalupa
发明人： Florian Bogenberger , Leos Chalupa
IPC分类号： G01R31/02
CPC分类号： G01R31/31701 , G01R31/31727
摘要： A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit. The system has a mode control unit containing a set of instructions which is executable by the logic circuit, for switching the logic circuit from and to a test mode in which a part of the logic circuit can be subjected to a selected test by executing a selected test routine.
摘要翻译：定时器单元包括用于定时逻辑电路处于自检模式的时间段的定时器。比较器连接到定时器，用于将逻辑电路允许处于自检模式的时间段中的最大值的时间与时间相比较，并且当时间段超过最大值时输出错误信号。测试定时器单元还包括用于检测逻辑电路到自检模式的切换的模式检测器。模式检测器连接到定时器，用于在切换到自检模式时启动定时器，并且在逻辑电路切换到自检模式之后停止定时器。定时器单元可用于测试逻辑电路的系统，该系统包括测试例程模块，该测试例程模块包含一组指令，该指令组形成用于在逻辑电路的测试部分上进行测试的测试程序。该系统具有包含可由逻辑电路执行的指令集的模式控制单元，用于将逻辑电路切换到测试模式，在测试模式中逻辑电路的一部分可以通过执行所选择的测试模式进行所选择的测试测试程序。

7. 发明授权

US09061589B2 Display controller, image processing system, display system, apparatus and computer program product 有权
标题翻译：显示控制器，图像处理系统，显示系统，设备和计算机程序产品
公开(公告)号：US09061589B2
公开(公告)日：2015-06-23
申请号：US12990868
申请日：2008-05-20
申请人： Florian Bogenberger , Davor Bogavac
发明人： Florian Bogenberger , Davor Bogavac
IPC分类号： G09G5/02 , B60K35/00 , G06F3/14 , G09G5/14
CPC分类号： B60K35/00 , B60K2350/1072 , B60K2350/2056 , G06F3/14 , G09G5/026 , G09G5/14 , G09G2330/12 , G09G2340/12 , G09G2380/10
摘要： A display controller includes a controller input connectable to receive first image data representing a non-safety relevant part of an image to be displayed on a display and to receive second image data representing a safety relevant part of the image. A merging unit is connected to the controller input, for composing the image from the first image data and second image data. A controller output is connectable to the display, for outputting display data representing the image. An image monitor is connected to the controller output, for comparing a part of the image corresponding to the safety relevant part with an reference for the part.
摘要翻译：显示控制器包括可连接以接收表示要显示在显示器上的图像的非安全相关部分的第一图像数据并且接收表示图像的安全相关部分的第二图像数据的控制器输入。合并单元连接到控制器输入，用于从第一图像数据和第二图像数据构成图像。控制器输出可连接到显示器，用于输出表示图像的显示数据。图像监视器连接到控制器输出，用于将与安全相关部分相对应的图像的一部分与部件的参考进行比较。

8. 发明申请

US20110214129A1 MANAGEMENT OF MULTIPLE RESOURCE PROVIDERS 有权
标题翻译：多资源提供者的管理
公开(公告)号：US20110214129A1
公开(公告)日：2011-09-01
申请号：US13128025
申请日：2008-11-24
申请人： Vladimir Litovtchenko , Florian Bogenberger
发明人： Vladimir Litovtchenko , Florian Bogenberger
IPC分类号： G06F9/50
CPC分类号： G06F9/505 , G06F2209/5019 , G06F2209/504 , Y02D10/22
摘要： A device receives a request for an amount of a resource. It determines for each resource provider in a set of resource providers a current load, a requested load corresponding to the requested amount of the resource, and an additional load corresponding to an expected state of an application. It determines for each of the resource providers an expected total load on the basis of the current load, the requested load, and the additional load. It subsequently selects from the set of resource providers a preferred resource provider on the basis of the expected total loads. The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device.
摘要翻译：设备接收到一个资源量的请求。它为资源提供者中的每个资源提供者确定当前负载，对应于所请求的资源量的请求负载以及对应于应用的预期状态的附加负载。它根据当前负载，请求的负载和附加负载来确定每个资源提供商预期的总负载。它随后根据预期的总负载从资源提供者组中选择优选的资源提供者。该资源可能是以下之一：存储器，处理时间，数据吞吐量，功率和设备的使用。

9. 发明申请

US20100011142A1 REQUEST CONTROLLER, PROCESSING UNIT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：请求控制器，处理单元，控制请求方法和计算机程序产品
公开(公告)号：US20100011142A1
公开(公告)日：2010-01-14
申请号：US12526306
申请日：2007-02-08
申请人： Florian Bogenberger , Vladimir A. Litovtchenko
发明人： Florian Bogenberger , Vladimir A. Litovtchenko
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the processing unit to switch a context of the processing unit or to switch the processing unit from a current an operation to another operation. The resource controller includes a resource budget memory in which one or more budget value can be stored. The budget value represents an amount of a resource of the processing unit. The resource controller further has a budget controller which includes a first budget controller input connected to the request controller input. A second budget controller input is connected to the memory. A comparator is connected to the first budget controller input and the second controller input, for comparing a consumption value associated with the request with the budget value. The comparator includes a comparator output for outputting a request grant signal when the comparison satisfies a predetermined grant criterion and outputting a request reject value when the comparison meets a predetermined reject criterion. A data controller is connected to the resource budget memory and the comparator output, for adjusting the budget value when the request grant signal is outputted.
摘要翻译：一种请求控制器，用于控制一个或多个半导体数据处理单元的请求处理。资源控制器包括控制器输入，用于接收处理单元切换处理单元的上下文的请求，或者将处理单元从当前操作切换到另一操作。资源控制器包括其中可以存储一个或多个预算值的资源预算存储器。预算值表示处理单元的资源量。资源控制器还具有预算控制器，其包括连接到请求控制器输入的第一预算控制器输入。第二个预算控制器输入连接到存储器。比较器连接到第一预算控制器输入和第二控制器输入，用于将与请求相关联的消耗值与预算值进行比较。比较器包括比较器输出，用于当比较满足预定的准许标准时输出请求授权信号，并且当比较满足预定的拒绝标准时输出请求拒绝值。数据控制器连接到资源预算存储器和比较器输出端，用于在输出请求授权信号时调整预算值。

10. 发明授权

US07586953B2 Method for monitoring a communication media access schedule of a communication controller of a communication system 失效
标题翻译：用于监视通信系统的通信控制器的通信介质访问调度的方法
公开(公告)号：US07586953B2
公开(公告)日：2009-09-08
申请号：US10613027
申请日：2003-07-07
申请人： Thomas Forest , Bernd Hedenetz , Mathias Rausch , Christopher Temple , Harald Eisele , Bernd Elend , Jörn Ungermann , Matthias Kühlewein , Ralf Belschner , Peter Lohrmann , Florian Bogenberger , Thomas Wuerz , Arnold Millsap , Patrick Heuts , Robert Hugel , Thomas Führer , Bernd Müller , Florian Hartwich , Manfred Zinke , Josef Berwanger , Christian Ebner , Harald Weiler , Peter Fuhrmann , Anton Schedl , Martin Peller
发明人： Thomas Forest , Bernd Hedenetz , Mathias Rausch , Christopher Temple , Harald Eisele , Bernd Elend , Jörn Ungermann , Matthias Kühlewein , Ralf Belschner , Peter Lohrmann , Florian Bogenberger , Thomas Wuerz , Arnold Millsap , Patrick Heuts , Robert Hugel , Thomas Führer , Bernd Müller , Florian Hartwich , Manfred Zinke , Josef Berwanger , Christian Ebner , Harald Weiler , Peter Fuhrmann , Anton Schedl , Martin Peller
IPC分类号： H04J3/06
CPC分类号： H04L12/40026 , H03M13/09 , H03M13/43 , H04J3/0652 , H04J3/0682 , H04J3/0694 , H04L7/0331 , H04L12/4035 , H04L12/417 , H04L12/44 , H04L12/6418 , H04L43/00 , H04L43/0847 , H04L2012/40241 , H04L2012/40273 , H04L2012/6435 , H04L2012/644 , H04L2012/6459
摘要： The invention refers to a method for monitoring a communication media access schedule of a communication controller (5) of a communication system (1) by means of a bus guardian (6). The communication system (1) comprises a communication media (2) and nodes (3) connected to the communication media (2). Each node (3) comprises a communication controller (5) and a bus guardian (6) assigned to the communication controller (5). Messages are transmitted among the nodes (3) across the communication media (2) based on a cyclic time triggered communication media access scheme. In order to provide a mechanism which allows the bus guardian (6) to monitor the communication media access scheme of the communication controller (5) even during startup of the communication it is suggested, that the bus guardian (6) has a priori knowledge about possible deviations from the communication media access schedule during startup of the communication and that the bus guardian (6) during startup makes use of the a priori knowledge to distinguish between an allowed deviation and a forbidden deviation caused by a failure of the communication controller (5).
摘要翻译：本发明涉及一种用于通过总线监控器（6）监视通信系统（1）的通信控制器（5）的通信介质访问调度的方法。通信系统（1）包括通信介质（2）和连接到通信介质（2）的节点（3）。每个节点（3）包括分配给通信控制器（5）的通信控制器（5）和总线监控器（6）。基于循环时间触发的通信媒体接入方案，在通信媒体（2）之间的节点（3）之间传送消息。为了提供一种允许总线监护人（6）甚至在通信启动期间监视通信控制器（5）的通信介质访问方案的机制，建议总线监护人（6）具有关于在通信启动期间与通信媒体访问调度的可能偏差，并且启动期间总线监控器（6）利用先验知识来区分由通信控制器（5）的故障引起的允许偏差和禁止偏差）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式