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1. 发明申请

US20060228876A1 Method of manufacturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060228876A1
公开(公告)日：2006-10-12
申请号：US11101639
申请日：2005-04-08
申请人： Olaf Storbeck , Jens Hahn , Sven Schmidbauer , Juergen Faul , Frank Jakubowski , Thomas Schuster
发明人： Olaf Storbeck , Jens Hahn , Sven Schmidbauer , Juergen Faul , Frank Jakubowski , Thomas Schuster
IPC分类号： H01L29/00
CPC分类号： H01L21/265 , H01L21/28044 , H01L21/324 , H01L29/4925
摘要： The invention relates to a method of manufacturing a semiconductor device, in which a substrate is provided, a dielectric layer is formed on top of the substrate, an amorphous semiconductor layer id deposited on top of the dielectric layer, the amorphous semiconductor layer is doped, and a high temperature step to the amorphous layer is applied to form a crystallized layer out of the amorphous semiconductor.
摘要翻译：本发明涉及一种制造半导体器件的方法，其中提供了一种衬底，在衬底的顶部形成介电层，淀积在电介质层顶部的非晶半导体层，掺杂非晶半导体层，并且施加到非晶层的高温步骤以从非晶半导体形成结晶层。

2. 发明申请

US20080124920A1 Fabrication method for an integrated circuit structure 审中-公开
标题翻译：集成电路结构的制造方法
公开(公告)号：US20080124920A1
公开(公告)日：2008-05-29
申请号：US11985067
申请日：2007-11-13
申请人： Clemens Fitz , Axel Buerke , Jens Hahn , Frank Jakubowski , Tobias Mono , Joern Regul , Sven Schmidbauer
发明人： Clemens Fitz , Axel Buerke , Jens Hahn , Frank Jakubowski , Tobias Mono , Joern Regul , Sven Schmidbauer
IPC分类号： H01L21/44
CPC分类号： H01L21/28247 , H01L21/28061 , H01L29/4941
摘要： The present invention provides a fabrication method for an integrated circuit structure comprising the steps of forming a electrode layer stack (5, 6′, 7′, 8′) by sequentially depositing a polysilicon layer (5) on a gate dielectric layer (9); a contact layer (6′) composed of Ti on the polysilicon layer (5); a barrier layer (7′) composed of WN on the contact layer (6′); and a metal layer (8′) composed of W on the barrier layer (7′); wherein steps iii) and iv) are carried out as PVD steps using krypton and/or xenon as sputtering gas; and annealing the layer stack (5, 6′, 7′, 8′) in a thermal step in the temperature range of between 600 and 950° C.
摘要翻译：本发明提供了一种用于集成电路结构的制造方法，包括以下步骤：通过在栅介电层（9）上依次沉积多晶硅层（5）形成电极层堆叠（5,6'，7'，8' ; 在多晶硅层（5）上由Ti构成的接触层（6'）; 在接触层（6'）上由WN组成的阻挡层（7'）; 和由阻挡层（7'）上的W构成的金属层（8'）。其中步骤iii）和iv）作为PVD步骤使用氪和/或氙作为溅射气体进行; 并且在600-950℃的温度范围内的热步骤中退火层堆叠（5,6'，7'，8'）。

3. 发明授权

US09023715B2 Methods of forming bulk FinFET devices so as to reduce punch through leakage currents 有权
标题翻译：形成散装FinFET器件的方法，以减少穿透漏电流
公开(公告)号：US09023715B2
公开(公告)日：2015-05-05
申请号：US13454520
申请日：2012-04-24
申请人： Juergen Faul , Frank Jakubowski
发明人： Juergen Faul , Frank Jakubowski
IPC分类号： H01L21/225 , H01L29/66
CPC分类号： H01L21/2255 , H01L29/66803
摘要： Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins.
摘要翻译：公开了形成体FinFET半导体器件以减少穿透漏电流的方法。一个实例包括在半导体衬底中形成多个沟槽以限定多个间隔开的散热片，在沟槽中形成绝缘材料的掺杂层，其中每个鳍的暴露部分在掺杂的上表面上方延伸绝缘材料层，而每个鳍片的覆盖部分位于绝缘材料的掺杂层的上表面的下方，并且进行加工操作以至少加热绝缘材料的掺杂层，以使掺杂物质掺杂层从绝缘材料的掺杂层迁移到鳍的被覆盖部分中，从而在翅片的被覆盖部分中限定位于翅片的暴露部分下方的掺杂区域。

4. 发明申请

US20130280883A1 METHODS OF FORMING BULK FINFET DEVICES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS 有权
标题翻译：形成散装FINFET器件的方法，以减少通过泄漏电流的冲击
公开(公告)号：US20130280883A1
公开(公告)日：2013-10-24
申请号：US13454520
申请日：2012-04-24
申请人： Juergen Faul , Frank Jakubowski
发明人： Juergen Faul , Frank Jakubowski
IPC分类号： H01L21/225
CPC分类号： H01L21/2255 , H01L29/66803
摘要： Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins.
摘要翻译：公开了形成体FinFET半导体器件以减少穿透漏电流的方法。一个实例包括在半导体衬底中形成多个沟槽以限定多个间隔开的散热片，在沟槽中形成绝缘材料的掺杂层，其中每个鳍的暴露部分在掺杂的上表面上方延伸绝缘材料层，而每个鳍片的覆盖部分位于绝缘材料的掺杂层的上表面的下方，并且进行加工操作以至少加热绝缘材料的掺杂层，以使掺杂物质掺杂层从绝缘材料的掺杂层迁移到鳍的被覆盖部分中，从而在翅片的被覆盖部分中限定位于翅片的暴露部分下方的掺杂区域。

5. 发明授权

US06967133B2 Method for fabricating a semiconductor structure 失效
标题翻译：半导体结构的制造方法
公开(公告)号：US06967133B2
公开(公告)日：2005-11-22
申请号：US10696159
申请日：2003-10-29
申请人： Jürgen Amon , Jürgen Faul , Ulrike Gruening , Frank Jakubowski , Thomas Schuster , Rudolf Strasser
发明人： Jürgen Amon , Jürgen Faul , Ulrike Gruening , Frank Jakubowski , Thomas Schuster , Rudolf Strasser
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L21/8242
CPC分类号： H01L27/10888 , H01L21/26586 , H01L21/28512 , H01L29/66659
摘要： The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).
摘要翻译：本发明提供了一种在半导体衬底（10）上制造具有多个栅极堆叠（GS 1，GS 2，GS 3，GS 4）的半导体结构的方法，具有以下步骤：施加栅极堆叠（GS 1，GS 2，GS 3，GS 4）连接到半导体衬底（10）上方的栅极电介质（11）; 在栅堆叠（GS 1，GS 2，GS 3，GS 4）的侧壁上形成侧壁氧化物（17）; 半导体结构上的掩模（12）的应用和图案化; 以及在未被掩模（12）覆盖的区域中相对于栅极堆叠（GS1，GS2）的侧壁氧化物（17）以自对准的方式注入接触掺杂（13）。

6. 发明申请

US20140051227A1 METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DRY CHEMICAL REMOVAL PROCESS 有权
标题翻译：通过实施干式化学除去工艺形成半导体器件的隔离结构的方法
公开(公告)号：US20140051227A1
公开(公告)日：2014-02-20
申请号：US13584981
申请日：2012-08-14
申请人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
发明人： Frank Jakubowski , Joerg Radecker , Joanna Wasyluk
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/02065 , H01L21/31053 , H01L21/31116
摘要： A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.
摘要翻译：一种方法包括形成图案化掩模，其由位于衬底上方的保护层上方的抛光停止层构成，通过衬底上的图案化掩模层执行至少一个蚀刻工艺，以在衬底中形成沟槽，并形成硅层在图案化掩模层之上的二氧化硅，使得二氧化硅层过度填充沟槽。该方法还包括去除位于沟槽外部的二氧化硅层的部分以限定隔离结构，执行干燥的选择性化学氧化物蚀刻工艺，其相对于抛光停止层的材料选择性地去除二氧化硅以减少整体隔离结构的高度，并且进行选择性湿蚀刻工艺以相对于隔离区选择性地去除抛光停止层。

7. 发明申请

US20130020656A1 HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION 有权
标题翻译：高性能HKMG堆栈进行第一次整合
公开(公告)号：US20130020656A1
公开(公告)日：2013-01-24
申请号：US13185112
申请日：2011-07-18
申请人： Frank Jakubowski , Peter Baars , Till Schloesser
发明人： Frank Jakubowski , Peter Baars , Till Schloesser
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/4966 , H01L29/7833
摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.
摘要翻译：半导体器件在功函数层与多晶硅之间形成硅化物界面。实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成硅化物上的多晶硅层。实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

8. 发明申请

US20080026530A1 Method of forming a doped portion of a semiconductor and method of forming a transistor 失效
标题翻译：形成半导体的掺杂部分的方法和形成晶体管的方法
公开(公告)号：US20080026530A1
公开(公告)日：2008-01-31
申请号：US11493028
申请日：2006-07-26
申请人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
发明人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26586 , H01L29/1045
摘要： A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.
摘要翻译：形成半导体衬底的掺杂部分的方法包括：在衬底表面上限定多个突起部分，突出部分具有最小高度; 在衬底表面上提供图案层; 从预定的基板部分去除图案层的部分; 执行离子注入过程，使得离子相对于衬底表面的角度小于90°，其中离子被图案层和突出部分停止，因此预定的衬底部分被掺杂了离子; 并去除图案层。

9. 发明授权

US07078748B2 Multi-layer gate stack structure comprising a metal layer for a FET device, and method for fabricating the same 失效
标题翻译：包括用于FET器件的金属层的多层栅极堆栈结构及其制造方法
公开(公告)号：US07078748B2
公开(公告)日：2006-07-18
申请号：US10865763
申请日：2004-06-14
申请人： Matthias Goldbach , Frank Jakubowski , Ralf Koepe , Chao-Wen Lay , Kristin Schupke , Michael Schmidt , Cheng-Chih Huang
发明人： Matthias Goldbach , Frank Jakubowski , Ralf Koepe , Chao-Wen Lay , Kristin Schupke , Michael Schmidt , Cheng-Chih Huang
IPC分类号： H01L27/148
CPC分类号： H01L21/28044
摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.
摘要翻译：通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中，过渡金属是钛，钽或钴。对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。在将多晶硅层图案化之前打开氮化物衬垫。作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

10. 发明授权

US08722523B2 Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure 有权
标题翻译：半导体器件包括自对准接触元件和替换栅电极结构
公开(公告)号：US08722523B2
公开(公告)日：2014-05-13
申请号：US13371049
申请日：2012-02-10
申请人： Till Schloesser , Peter Baars , Frank Jakubowski
发明人： Till Schloesser , Peter Baars , Frank Jakubowski
IPC分类号： H01L29/772
CPC分类号： H01L29/78 , H01L21/28518 , H01L21/28525 , H01L21/288 , H01L21/76816 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.
摘要翻译：当形成包括高k金属栅电极结构的复杂半导体器件时，可以使用升高的漏极和源极配置来控制在执行替代栅极接近时的高度，从而为形成接触元件提供优越的条件，并且还获得良好可控的减小的门高。

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