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1. 发明授权

US4986666A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4986666A
公开(公告)日：1991-01-22
申请号：US277261
申请日：1988-11-29
申请人： Noriyuki Homma , Hisayuki Higuchi , Yoji Idei , Hiroaki Nambu , Yoshiaki Sakurai
发明人： Noriyuki Homma , Hisayuki Higuchi , Yoji Idei , Hiroaki Nambu , Yoshiaki Sakurai
IPC分类号： G11C7/06 , G11C7/10 , G11C8/10 , G11C11/416
CPC分类号： G11C7/1057 , G11C11/416 , G11C7/062 , G11C7/065 , G11C7/1039 , G11C7/1051 , G11C8/10
摘要： A semiconductor memory device capable of operating at high speeds, and a sense circuit and a decoder circuit that can be suitably used for the memory device. A latch function is imparted to at least either one of the decoder circuit or the sense circuit in the semiconductor memory device.
摘要翻译：能够高速运行的半导体存储器件，以及适用于存储器件的读出电路和解码器电路。锁存功能被赋予半导体存储器件中的解码器电路或感测电路中的至少一个。

2. 发明授权

US08174907B2 Semiconductor device having data input/output unit connected to bus line 有权
标题翻译：具有连接到总线的数据输入/输出单元的半导体器件
公开(公告)号：US08174907B2
公开(公告)日：2012-05-08
申请号：US12763741
申请日：2010-04-20
申请人： Takuyo Kodama , Yoji Idei
发明人： Takuyo Kodama , Yoji Idei
IPC分类号： G11C7/10
CPC分类号： G11C11/4094 , G11C7/1006 , G11C7/1012 , G11C7/1048 , G11C11/4096 , G11C11/4097
摘要： To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like.
摘要翻译：提供一种半导体器件，包括：第一和第二总线; 连接在第一和第二总线之间的第一缓冲器; 连接到第一总线的第二和第三缓冲器; 连接到第二总线的第四和第五缓冲器; 经由第一，第二和第三缓冲器连接到第二总线的第一至第四组; 经由第四和第五缓冲器连接到第二总线的第五至第八组; 以及连接到第二总线的数据输入/输出单元。第四和第五缓冲器的传输延迟时间长于第一，第二和第三缓冲器的传输延迟时间。由此，可以消除由于近端和近端之间的距离的差异导致的数据传输时间的差异，而不会导致线密度的显着增加，功率消耗的增加等。

3. 发明授权

US07889584B2 Semiconductor memory device having input first-stage circuit 有权
标题翻译：具有输入第一级电路的半导体存储器件
公开(公告)号：US07889584B2
公开(公告)日：2011-02-15
申请号：US11580275
申请日：2006-10-13
申请人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
发明人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
IPC分类号： G11C7/02
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.
摘要翻译：本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

4. 发明授权

US07675347B2 Semiconductor device operating in an active mode and a standby mode 失效
标题翻译：半导体器件工作在主动模式和待机模式
公开(公告)号：US07675347B2
公开(公告)日：2010-03-09
申请号：US11984464
申请日：2007-11-19
申请人： Kazuhiro Teramoto , Yoji Idei
发明人： Kazuhiro Teramoto , Yoji Idei
IPC分类号： H03K3/01
CPC分类号： H03K3/356113 , H03K19/0016 , H03K2217/0018
摘要： A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.
摘要翻译：半导体器件以活动模式或待机模式工作，并且包括提供在待机模式下比在活动模式中更高的衬底电位的衬底电位电源线以及提供源的源极 - 电位电源线待机模式下的电位低于活动模式。在从待机模式切换到激活模式的模式期间，电位均衡晶体管导通以使从衬底电位电源线流到源极电源线的电流通过，以减少移位所需的时间长度从待机模式到活动模式。

5. 发明申请

US20090016126A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20090016126A1
公开(公告)日：2009-01-15
申请号：US12170561
申请日：2008-07-10
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C29/02 , G11C29/025 , G11C29/50008 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.
摘要翻译：提供一种半导体存储器件，其能够检测在存储器阵列中要检测的短路缺陷，而不会由于读出放大器电路的截止电流而引起误差。感测放大器电路根据通过驱动字线和位线选择的存储器单元的电位放大一对位线之间的电位。选择晶体管设置在位线和读出放大器电路之间。包括在X定时发生电路中的字SE间隔控制电路关闭选择晶体管，并且当扩展字线之间的间隔的测试时，基于表示用于扩展时间的测试状态的信号，从读出放大器电路断开位线执行感测放大器电路的驱动和激活并检测位线的缺陷位置。

6. 发明授权

US07719911B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07719911B2
公开(公告)日：2010-05-18
申请号：US12169873
申请日：2008-07-09
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G11C7/08 , G11C11/4091
摘要： A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.
摘要翻译：提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

7. 发明申请

US20080116956A1 Semiconductor device operating in an active mode and a standby mode 失效
标题翻译：半导体器件工作在主动模式和待机模式
公开(公告)号：US20080116956A1
公开(公告)日：2008-05-22
申请号：US11984464
申请日：2007-11-19
申请人： Kazuhiro Teramoto , Yoji Idei
发明人： Kazuhiro Teramoto , Yoji Idei
IPC分类号： H03K3/01
CPC分类号： H03K3/356113 , H03K19/0016 , H03K2217/0018
摘要： A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.
摘要翻译：半导体器件以活动模式或待机模式工作，并且包括提供在待机模式下比在活动模式中更高的衬底电位的衬底电位电源线以及提供源的源极 - 电位电源线待机模式下的电位低于活动模式。在从待机模式切换到激活模式的模式期间，电位均衡晶体管导通以使从衬底电位电源线流到源极电源线的电流通过，以减少移位所需的时间长度从待机模式到活动模式。

8. 发明授权

US06867626B2 Clock synchronization circuit having bidirectional delay circuit strings and controllable pre and post stage delay circuits connected thereto and semiconductor device manufactured thereof 失效
标题翻译：时钟同步电路具有双向延迟电路串和与其连接的可控的前级和后级延迟电路及其制造的半导体器件
公开(公告)号：US06867626B2
公开(公告)日：2005-03-15
申请号：US10624801
申请日：2003-07-22
申请人： Yoji Idei
发明人： Yoji Idei
IPC分类号： G06F1/10 , G11C7/22 , G11C11/407 , G11C11/4076 , H03K5/13 , H03K5/131 , H03L7/00
CPC分类号： G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the first bidirectional delay circuit string (BDDA), a second pre-stage delay circuit and a second post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the second bidirectional delay circuit string (BDDB), and a multiplexer, supplied with and multiplexing outputs of the first and second post-stage delay circuits to output the resulting signals. An output signal of the first delay circuit is supplied in common to the first and second pre-stage delay circuits. A first path composed of the first pre-stage delay circuit, first bidirectional delay circuit string and the first post-stage delay circuit and a second path composed of the second pre-stage delay circuit, second bidirectional delay circuit string and the second post-stage delay circuit are alternately switched in an interval of one cycle of the clock signal.
摘要翻译：时钟同步电路包括用于延迟时钟信号并输出延迟的时钟信号的第一延迟电路，第一和第二双向延迟电路串，可变延迟时间类型的第一前级延迟电路和第一后级延迟电路，布置在前级和后级的第一双向延迟电路串（BDDA），第二预延迟电路和可变延迟时间类型的第二后级延迟电路，布置在前级和第二双向延迟电路串（BDDB）的后级，以及多路复用器，提供并复用第一和第二后级延迟电路的输出，以输出结果信号。第一延迟电路的输出信号被共同地提供给第一和第二前级延迟电路。由第一前级延迟电路，第一双向延迟电路串和第一后级延迟电路组成的第一路径和由第二前级延迟电路，第二双向延迟电路串和第二后级延迟电路组成的第二路径，在时钟信号的一个周期的间隔中交替地切换级延迟电路。

9. 发明授权

US6067257A Semiconductor integrated circuit device having step-down voltage circuit 有权
标题翻译：具有降压电压电路的半导体集成电路器件
公开(公告)号：US6067257A
公开(公告)日：2000-05-23
申请号：US270677
申请日：1999-03-16
申请人： Goro Kitsukawa , Yoji Idei
发明人： Goro Kitsukawa , Yoji Idei
IPC分类号： G11C5/14 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/147 , G11C11/4074
摘要： A semiconductor integrated circuit device is provided with an internal circuit which receives a source voltage supplied from an external terminal and is activated based on a voltage obtained by reducing the source voltage, and an output circuit which outputs a signal to be outputted produced by the internal circuit, through an external terminal in accordance with a timing signal. In the semiconductor integrated circuit device, a level shift circuit converts the signal produced by the internal circuit to a signal level corresponding to the level of the source voltage supplied from the external terminal. The output circuit outputs the level-shifted signal therefrom using a timing signal of a voltage level corresponding to the source voltage supplied from the external terminal.
摘要翻译：半导体集成电路器件具有内部电路，该内部电路接收从外部端子提供的源极电压，并且基于通过降低源极电压获得的电压而被激活;以及输出电路，其输出由内部产生的输出信号电路，通过外部端子根据定时信号。在半导体集成电路装置中，电平移位电路将由内部电路产生的信号转换为与从外部端子提供的源极电压的电平相对应的信号电平。输出电路使用与从外部端子提供的源极电压相对应的电压电平的定时信号输出电平移位信号。

10. 发明授权

US07863969B2 Power supply voltage dropping circuit using an N-channel transistor output stage 有权
标题翻译：使用N沟道晶体管输出级的电源降压电路
公开(公告)号：US07863969B2
公开(公告)日：2011-01-04
申请号：US12435780
申请日：2009-05-05
申请人： Ryohei Furuya , Yoji Idei
发明人： Ryohei Furuya , Yoji Idei
IPC分类号： G05F1/563 , H02M3/00
CPC分类号： G05F1/563
摘要： A device includes an N-channel transistor for output, a voltage raising circuit, a voltage dropping circuit, and an amplifier. A power supply voltage that is a first voltage is supplied to one end of the output N-channel transistor, and the other end of the output N-channel transistor functions as an output terminal. The voltage raising circuit raises the first voltage to generate a second voltage higher than the first voltage. The voltage dropping circuit reduces the second voltage to generate a third voltage that is higher than the first voltage and is lower than the second voltage. The amplifier amplifies the difference between a reference voltage and a voltage generated at the output terminal, using the third voltage as a power supply voltage, to generate a fourth voltage, and supplies the fourth voltage to the gate of the N-channel transistor for output.
摘要翻译：一种器件包括用于输出的N沟道晶体管，升压电路，降压电路和放大器。作为第一电压的电源电压被提供给输出N沟道晶体管的一端，输出N沟道晶体管的另一端用作输出端子。升压电路升高第一电压以产生高于第一电压的第二电压。降压电路降低第二电压以产生比第一电压高的第三电压并且低于第二电压。该放大器利用第三电压作为电源电压来放大参考电压和在输出端产生的电压之间的差，以产生第四电压，并将第四电压提供给N沟道晶体管的栅极用于输出。

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