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1. 发明申请

US20070085601A1 Semiconductor memory device and memory module 有权
标题翻译：半导体存储器件和存储器模块
公开(公告)号：US20070085601A1
公开(公告)日：2007-04-19
申请号：US11580275
申请日：2006-10-13
申请人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
发明人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
IPC分类号： H03B1/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.
摘要翻译：本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

2. 发明授权

US07889584B2 Semiconductor memory device having input first-stage circuit 有权
标题翻译：具有输入第一级电路的半导体存储器件
公开(公告)号：US07889584B2
公开(公告)日：2011-02-15
申请号：US11580275
申请日：2006-10-13
申请人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
发明人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
IPC分类号： G11C7/02
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.
摘要翻译：本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

3. 发明授权

US07760531B2 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US07760531B2
公开(公告)日：2010-07-20
申请号：US11511262
申请日：2006-08-29
申请人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
发明人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
IPC分类号： G11C5/02
CPC分类号： G11C5/147 , G11C5/02 , G11C7/02 , H01L24/48 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2924/00014 , H01L2924/10161 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.
摘要翻译：半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。第一半导体器件包括第一电极。第二半导体器件包括第二电极。参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

4. 发明授权

US07768867B2 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US07768867B2
公开(公告)日：2010-08-03
申请号：US11761470
申请日：2007-06-12
申请人： Yoji Nishio , Yutaka Uematsu , Seiji Funaba , Hideki Osaka , Tsutomu Hara , Koichiro Aoki
发明人： Yoji Nishio , Yutaka Uematsu , Seiji Funaba , Hideki Osaka , Tsutomu Hara , Koichiro Aoki
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C5/02 , G11C5/04 , H01L25/105 , H01L2924/0002 , H01L2924/15311 , H01L2924/15331 , H01L2924/00
摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.
摘要翻译：叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。数据选通信号和反相数据选通信号相互配合。用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘存储芯片12。

5. 发明申请

US20070047354A1 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US20070047354A1
公开(公告)日：2007-03-01
申请号：US11511262
申请日：2006-08-29
申请人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
发明人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
IPC分类号： G11C7/02
CPC分类号： G11C5/147 , G11C5/02 , G11C7/02 , H01L24/48 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2924/00014 , H01L2924/10161 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.
摘要翻译：半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。第一半导体器件包括第一电极。第二半导体器件包括第二电极。参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

6. 发明授权

US07447038B2 Module 有权
标题翻译：模块
公开(公告)号：US07447038B2
公开(公告)日：2008-11-04
申请号：US11304625
申请日：2005-12-16
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
IPC分类号： H05K1/00
CPC分类号： H05K1/023 , H01L23/50 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/48472 , H01L2224/49 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/0227 , H05K1/0231 , H05K1/0233 , H05K1/025 , H05K1/181 , H05K2201/093 , H05K2201/09663 , H05K2201/10022 , H05K2201/1003 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.
摘要翻译：在存储器模块中，多个存储器安装在模块基板上，每个存储器附近的Vref和Vss之间的阻抗通过去耦电容器和Vref平面耦合到Vss，以在宽的频率范围内实现低阻抗配置，Vref平面分别提供给各个存储器，并且Vref平面通过使用高阻抗线或高阻抗芯片部分彼此连接。因此，可以提供一种能够有效降低自身噪声和传播噪声的用于模块的布线技术。

7. 发明申请

US20080054379A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080054379A1
公开(公告)日：2008-03-06
申请号：US11675476
申请日：2007-02-15
申请人： Yoji Nishio , Yutaka Uematsu , Hideki Osaka , Tsutomu Hara , Seiji Funaba
发明人： Yoji Nishio , Yutaka Uematsu , Hideki Osaka , Tsutomu Hara , Seiji Funaba
IPC分类号： H01L29/94
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/109
摘要： Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.
摘要翻译：输入电路确保参考电压的噪声容限。半导体芯片11a包括输入参考电压Vref的焊盘14，连接在输入电路13的输入端子和焊盘14之间的电阻元件R 1，连接在输入端13之间的电容元件C 1 输入电路13的端子和电源VDD，以及连接在输入电路13的输入端子和半导体芯片内的接地VSS之间的电容元件C 2。基于网络的阻抗特性来设定电阻元件R 1的电阻值，用于提供基准电压Vref。

8. 发明申请

US20060133055A1 Module 有权
标题翻译：模块
公开(公告)号：US20060133055A1
公开(公告)日：2006-06-22
申请号：US11304625
申请日：2005-12-16
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
IPC分类号： H05K7/08
CPC分类号： H05K1/023 , H01L23/50 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/48472 , H01L2224/49 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/0227 , H05K1/0231 , H05K1/0233 , H05K1/025 , H05K1/181 , H05K2201/093 , H05K2201/09663 , H05K2201/10022 , H05K2201/1003 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.
摘要翻译：在存储器模块中，多个存储器安装在模块基板上，每个存储器附近的Vref和Vss之间的阻抗通过去耦电容器和Vref平面耦合到Vss，以在宽的频率范围内实现低阻抗配置，Vref平面分别提供给各个存储器，并且Vref平面通过使用高阻抗线或高阻抗芯片部分彼此连接。因此，可以提供一种能够有效降低自身噪声和传播噪声的用于模块的布线技术。

9. 发明授权

US07411806B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07411806B2
公开(公告)日：2008-08-12
申请号：US11634405
申请日：2006-12-06
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

10. 发明申请

US20060006516A1 Stacked semiconductor device and semiconductor memory module 有权
标题翻译：堆叠半导体器件和半导体存储器模块
公开(公告)号：US20060006516A1
公开(公告)日：2006-01-12
申请号：US11176292
申请日：2005-07-08
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： H01L23/02
CPC分类号： H01L23/66 , G11C5/04 , G11C5/063 , H01L24/06 , H01L24/49 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06136 , H01L2224/49171 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.
摘要翻译：半导体器件模块包括布线基板，多个堆叠半导体器件和阻尼阻抗电路。多个堆叠的半导体器件设置在布线基板上，并且以简单的方式与信号连接，并且多个堆叠的半导体器件中的每一个包括堆叠的多个半导体芯片。阻尼阻抗电路被设置为用于作为多个半导体器件中的一个堆叠半导体器件的第一堆叠半导体器件的多个半导体芯片中的最上半个半导体芯片的信号的距离布线基板的最远的信号的传输路径，首先提供信号。

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