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1. 发明授权

US07688649B2 Semiconductor memory device with debounced write control signal 失效
标题翻译：具有去抖动写入控制信号的半导体存储器件
公开(公告)号：US07688649B2
公开(公告)日：2010-03-30
申请号：US12073751
申请日：2008-03-10
申请人： Noriyoshi Sato , Nobutaka Nasu , Tetsuya Tanabe
发明人： Noriyoshi Sato , Nobutaka Nasu , Tetsuya Tanabe
IPC分类号： G11C7/00
CPC分类号： G11C17/16 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C11/4096 , G11C17/18
摘要： A semiconductor memory device having a memory cell array, an input buffer, an output buffer, and an input-output control circuit that receives a write control signal and controls the input and output buffers. The output buffer generates a commencement signal indicating commencement of output. A mask generating circuit generates a mask signal with delayed active-to-inactive transitions from the commencement signal. A masking circuit passes the write control signal to the input-output control circuit while the mask signal is inactive, and holds the write control signal in the write-disabling state while the mask signal is active. The mask signal prevents unintended writing of data in the memory cell array when the write control signal is contaminated by noise from the output buffer.
摘要翻译：具有存储单元阵列，输入缓冲器，输出缓冲器和输入输出控制电路的半导体存储器件，其接收写入控制信号并控制输入和输出缓冲器。输出缓冲器生成表示输出开始的开始信号。掩模产生电路从起始信号产生具有延迟的有效到无效转换的屏蔽信号。当屏蔽信号无效时，屏蔽电路将写入控制信号传递到输入 - 输出控制电路，并且在屏蔽信号有效时将写入控制信号保持在写入禁止状态。当写控制信号被来自输出缓冲器的噪声污染时，掩模信号防止数据在存储单元阵列中的意外写入。

2. 发明申请

US20080165597A1 Semiconductor memory device with debounced write control signal 失效
标题翻译：具有去抖动写入控制信号的半导体存储器件
公开(公告)号：US20080165597A1
公开(公告)日：2008-07-10
申请号：US12073751
申请日：2008-03-10
申请人： Noriyoshi Sato , Nobutaka Nasu , Tetsuya Tanabe
发明人： Noriyoshi Sato , Nobutaka Nasu , Tetsuya Tanabe
IPC分类号： G11C7/10
CPC分类号： G11C17/16 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C11/4096 , G11C17/18
摘要： A semiconductor memory device having a memory cell array, an input buffer, an output buffer, and an input-output control circuit that receives a write control signal and controls the input and output buffers. The output buffer generates a commencement signal indicating commencement of output. A mask generating circuit generates a mask signal with delayed active-to-inactive transitions from the commencement signal. A masking circuit passes the write control signal to the input-output control circuit while the mask signal is inactive, and holds the write control signal in the write-disabling state while the mask signal is active. The mask signal prevents unintended writing of data in the memory cell array when the write control signal is contaminated by noise from the output buffer.
摘要翻译：具有存储单元阵列，输入缓冲器，输出缓冲器和输入输出控制电路的半导体存储器件，其接收写入控制信号并控制输入和输出缓冲器。输出缓冲器生成表示输出开始的开始信号。掩模产生电路从起始信号产生具有延迟的有效到无效转换的屏蔽信号。当屏蔽信号无效时，屏蔽电路将写入控制信号传递到输入 - 输出控制电路，并且在屏蔽信号有效时将写入控制信号保持在写入禁止状态。当写控制信号被来自输出缓冲器的噪声污染时，掩模信号防止数据在存储单元阵列中的意外写入。

3. 发明申请

US20060285183A1 Semiconductor memory device with debounced write control signal 审中-公开
标题翻译：具有去抖动写入控制信号的半导体存储器件
公开(公告)号：US20060285183A1
公开(公告)日：2006-12-21
申请号：US11438228
申请日：2006-05-23
申请人： Noriyoshi Sato , Nobutaka Nasu , Tetsuya Tanabe
发明人： Noriyoshi Sato , Nobutaka Nasu , Tetsuya Tanabe
IPC分类号： H04N1/46
CPC分类号： G11C17/16 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C11/4096 , G11C17/18
摘要： A semiconductor memory device having a memory cell array, an input buffer, an output buffer, and an input-output control circuit that receives a write control signal and controls the input and output buffers. The output buffer generates a commencement signal indicating commencement of output. A mask generating circuit generates a mask signal with delayed active-to-inactive transitions from the commencement signal. A masking circuit passes the write control signal to the input-output control circuit while the mask signal is inactive, and holds the write control signal in the write-disabling state while the mask signal is active. The mask signal prevents unintended writing of data in the memory cell array when the write control signal is contaminated by noise from the output buffer.
摘要翻译：具有存储单元阵列，输入缓冲器，输出缓冲器和输入输出控制电路的半导体存储器件，其接收写入控制信号并控制输入和输出缓冲器。输出缓冲器生成表示输出开始的开始信号。掩模产生电路从起始信号产生具有延迟的有效到无效转换的屏蔽信号。当屏蔽信号无效时，屏蔽电路将写入控制信号传递到输入 - 输出控制电路，并且在屏蔽信号有效时将写入控制信号保持在写入禁止状态。当写控制信号被来自输出缓冲器的噪声污染时，掩模信号防止数据在存储单元阵列中的意外写入。

4. 发明授权

US06868021B2 Rapidly testable semiconductor memory device 有权
标题翻译：快速测试的半导体存储器件
公开(公告)号：US06868021B2
公开(公告)日：2005-03-15
申请号：US10669532
申请日：2003-09-25
申请人： Tetsuya Tanabe , Nobutaka Nasu
发明人： Tetsuya Tanabe , Nobutaka Nasu
IPC分类号： G11C29/00 , G11C29/44 , G11C7/00
CPC分类号： G11C29/781 , G11C29/1201 , G11C29/44 , G11C29/846
摘要： A semiconductor memory device has an array of memory cells, an array of sense amplifiers selected at least two at a time by column lines, data bus lines that receive data read from the memory cell array by the selected sense amplifiers, a decision circuit that compares data read by two of the selected sense amplifiers, and an input-output buffer. Normally, the input-output buffer receives and outputs data from one or more of the data bus lines. In a test output mode, the input-output buffer receives and outputs comparison result data from the decision circuit. In a semiconductor memory device with multiple memory cell arrays, this arrangement enables data read from different memory cells in the same memory cell array to be compared, so that redundancy repair can be carried out efficiently.
摘要翻译：一种半导体存储器件具有存储单元阵列，一列由列线一次至少选择两个的读出放大器阵列，接收由所选择的读出放大器从存储单元阵列读取的数据的数据总线线路，比较由所选择的读出放大器中的两个读取的数据以及输入 - 输出缓冲器。通常，输入 - 输出缓冲器从一个或多个数据总线接收并输出数据。在测试输出模式下，输入 - 输出缓冲器从判定电路接收并输出比较结果数据。在具有多个存储单元阵列的半导体存储器件中，这种布置使得可以比较在相同存储单元阵列中从不同存储单元读取数据，从而可以有效地执行冗余修复。

5. 发明授权

US06304508B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06304508B1
公开(公告)日：2001-10-16
申请号：US09519573
申请日：2000-03-06
申请人： Hidenori Uehara , Nobutaka Nasu
发明人： Hidenori Uehara , Nobutaka Nasu
IPC分类号： G11C700
CPC分类号： G11C5/145 , G11C8/08
摘要： A semiconductor device includes an internal source voltage generating circuit (debooster circuit) provided between an external source voltage EVCC and a ground voltage VSS and for generating an internal source voltage IVCC necessary to drive each of internal circuits in the semiconductor device, a booster circuit provided between the internal source voltage IVCC and the ground voltage VSS, for generating a boosted voltage VBST higher than the internal source voltage IVCC, and a capacitor provided between the boosted voltage VBST and the ground voltage, for stabilizing the boosted voltage VBST. The capacitor comprises a P type semiconductor substrate to which the ground voltage is applied, and an N type well region having therein a P type well region with a memory cell formed therein and to which the internal source voltage IVCC is applied.
摘要翻译：半导体器件包括设置在外部源电压EVCC和接地电压VSS之间的内部源极电压发生电路（去激励电路），并且用于产生驱动半导体器件中的每个内部电路所需的内部源极电压IVCC，提供的升压电路在内部源极电压IVCC和接地电压VSS之间产生用于产生比内部源极电压IVCC高的升压电压VBST，以及设置在升压电压VBST和接地电压之间的电容器，用于稳定升压电压VBST。电容器包括施加接地电压的P型半导体衬底和其中具有存储单元的P型阱区的N型阱区，并且施加有内部源极电压IVCC。

6. 发明授权

US07869245B2 Semiconductor storage device with first and second pads arranged in proximity with first to fourth output transistors for reducing an excess region 有权
标题翻译：具有第一和第二焊盘的半导体存储装置，其布置在第一至第四输出晶体管附近以减少过量区域
公开(公告)号：US07869245B2
公开(公告)日：2011-01-11
申请号：US11938913
申请日：2007-11-13
申请人： Nobutaka Nasu
发明人： Nobutaka Nasu
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , G11C5/025 , H01L24/06 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： An excess region on a chip plane is eliminated to reduce a chip size. A plurality of data pads, which input/output data, are arranged near one side of an outer periphery of a substrate in parallel with the aforementioned one side, and a plurality of data pads, which input/output data, are arranged on an inner side of the plurality of data pads in parallel with the plurality of data pads. NMOSs, which output data, are arranged between the data pads, and PMOSs, which output data, are arranged at positions where they face the NMOSs near the data pads.
摘要翻译：消除芯片平面上的多余区域以减小芯片尺寸。多个数据焊盘，其输入/输出数据被布置在与上述一侧平行的衬底的外周的一侧附近，并且多个数据焊盘，该输入/输出数据被布置在内部所述多个数据焊盘的一侧与所述多个数据焊盘并联。输出数据的NMOS被布置在数据焊盘之间，并且输出数据的PMOS被布置在它们靠近数据焊盘的NMOS的位置处。

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