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1. 发明授权

US4392219A Method and device for recording and reproducing tracking information 失效
标题翻译：用于记录和再现跟踪信息的方法和装置
公开(公告)号：US4392219A
公开(公告)日：1983-07-05
申请号：US252593
申请日：1981-04-09
申请人： Norio Yokozawa , Wasao Takasugi , Seiji Yonezawa , Kiichi Ueyanagi
发明人： Norio Yokozawa , Wasao Takasugi , Seiji Yonezawa , Kiichi Ueyanagi
IPC分类号： H04N5/85 , G11B7/09 , G11B21/10
CPC分类号： G11B7/0938 , G11B21/10
摘要： A method for recording and reproducing information characterized in that an information train in which synchronizing signals are arrayed at equal time intervals between information signals is recorded in an information track on a recording medium which is wobbled in synchronism with the synchronizing signals and at a frequency integral times the frequency of the synchronizing signals, that the information train recorded in the information track is read out by read-out means, and that a position of the read-out means is controlled on the basis of the information train read out. The wobbling waveform is 90.degree. out of phase with a harmonic component of the synchronizing signals.
摘要翻译：一种用于记录和再现信息的方法，其特征在于，在信息信号之间以相等的时间间隔排列同步信号的信息列被记录在与同步信号同步地摆动的记录介质上的信息轨道中，并以频率积分乘以同步信号的频率，通过读出装置读出记录在信息轨道中的信息列，并且基于读出的信息列来控制读出装置的位置。摆动波形与同步信号的谐波分量相差90°。

2. 发明授权

US4282551A PCM Recording and reproducing apparatus 失效
标题翻译： PCM录音和再现设备
公开(公告)号：US4282551A
公开(公告)日：1981-08-04
申请号：US138275
申请日：1980-04-09
申请人： Yasunori Kanazawa , Takao Arai , Norio Yokozawa , Wasao Takasugi
发明人： Yasunori Kanazawa , Takao Arai , Norio Yokozawa , Wasao Takasugi
IPC分类号： G11B20/18 , G11B5/00 , G11B5/09
CPC分类号： G11B20/1813
摘要： When error detection codes are added to a sampled signal word which is a digital version of audio information and a control signal which is a digital version of system control information to construct a data frame and a control signal frame, respectively, the error detection code for the data frame is generated under an arithmetic condition different from that for the control signal frame. In this manner, frame identification information is superimposed on the error detection codes. In a reproducing unit, the error detection codes containing the identification information are used to check an error in the reproduced sampled signal word and control signal and to effect the discrimination between the data frame and the control signal frame.
摘要翻译：当将错误检测码添加到作为音频信息的数字版本的采样信号字和分别构成数据帧和控制信号帧的系统控制信息的数字版本的控制信号时，分别用于在与控制信号帧不同的算术条件下生成数据帧。以这种方式，帧识别信息叠加在错误检测码上。在再现单元中，包含识别信息的检错码用于检查再现的采样信号字和控制信号中的错误，并且实现数据帧与控制信号帧之间的鉴别。

3. 发明授权

US4680498A Input circuit in ultrasonic apparatus 失效
标题翻译：超声波设备输入电路
公开(公告)号：US4680498A
公开(公告)日：1987-07-14
申请号：US827602
申请日：1986-02-10
申请人： Wasao Takasugi , Ryuichi Shinomura , Norio Yokozawa
发明人： Wasao Takasugi , Ryuichi Shinomura , Norio Yokozawa
IPC分类号： A61B8/00 , G01H11/08 , G01N29/44 , H01L41/08
CPC分类号： G01H11/08
摘要： An input circuit in which an input impedance of a reception amplifier connected to a piezoelectric transducer is selected to be lower than an impedance composed of an inter-electrode capacitance of the piezoelectric transducer, an equivalent capacitance of a cable used to connect the piezoelectric transducer to the reception amplifier, etc., that is, the parallel impedance of those elements connected in parallel to the reception amplifier so that the reception amplifier is used as an amplifier of the current detection type.
摘要翻译：一种输入电路，其中连接到压电换能器的接收放大器的输入阻抗被选择为低于由压电换能器的电极间电容构成的阻抗，用于将压电换能器连接到的电缆的等效电容接收放大器等，即与接收放大器并联连接的那些元件的并联阻抗，使得接收放大器用作当前检测类型的放大器。

4. 发明授权

US4051457A System for generating a character pattern 失效
标题翻译：用于生成字符模式的系统
公开(公告)号：US4051457A
公开(公告)日：1977-09-27
申请号：US655139
申请日：1976-02-03
申请人： Fumiyuki Inose , Kenji Fujikata , Norio Yokozawa
发明人： Fumiyuki Inose , Kenji Fujikata , Norio Yokozawa
IPC分类号： G11B20/00 , G06F3/153 , G06K15/10 , G09G1/02 , G09G5/24 , H03M7/00 , G11C15/00
CPC分类号： H03M7/001 , G09G1/02
摘要： In a character displaying device having a character pattern memory which is made up of a circulating sequential access memory storing character patterns therein, a character pattern generating system comprises a high speed buffer memory which stores the character codes of one line or any other suitable amount of characters to be displayed and the corresponding character patterns, so that each time one character is delivered as an output from the character pattern memory, the presence of the character code of the particular character is examined for all the character codes of the buffer memory, and the character pattern of the particular character is written into the buffer memory when the character codes are coincident, the writing operations being sequentially executed in the order of the character outputs of the character pattern memory, thereby making it possible to finish all the character patterns in the buffer memory within a period in which the read-out of the character pattern memory circulates.

5. 发明授权

US4389711A Touch sensitive tablet using force detection 失效
标题翻译：使用力检测触摸敏感平板电脑
公开(公告)号：US4389711A
公开(公告)日：1983-06-21
申请号：US177058
申请日：1980-08-11
申请人： Masao Hotta , Yoshikazu Miyamoto , Norio Yokozawa , Yoshimitsu Oshima
发明人： Masao Hotta , Yoshikazu Miyamoto , Norio Yokozawa , Yoshimitsu Oshima
IPC分类号： G06F3/033 , G06F3/041 , G08C21/00
CPC分类号： G06F3/0414
摘要： A tablet comprising conversion means to convert component forces at three fulcra of an external force applied to one point on a faceplate into electric signals, sensing means to sense that no external force is applied, memory means to store the output signals of the conversion means at the respective fulcra as offset values at, at least, one point of time in the period in which no external force is applied, control means to control so as to execute writing into the memory means upon receiving an output of the sensing means, subtraction means to subtract outputs of the memory means from the outputs of the conversion means at the respective fulcra, and calculation means to execute calculations for evaluating coordinates of the point to which the external force has been applied, from outputs of the subtraction means in accordance with the output of the sensing means.
摘要翻译：一种平板电脑，包括转换装置，用于将施加到面板上的一个点的外力的三个支点的分量力转换为电信号，感测装置，以感测不施加外力;存储装置，用于将转换装置的输出信号存储在在不施加外力的期间内的至少一个时间点的各自的支点作为偏移值，控制装置进行控制，以便在接收到感测装置的输出时执行写入存储装置，减法装置根据相应的支点从转换装置的输出中减去存储装置的输出;以及计算装置，根据减法装置的输出执行用于评估施加了外力的点的坐标的计算感测装置的输出。

6. 发明授权

US4293819A High-speed low-drift operational amplifier 失效
标题翻译：高速低漂移运算放大器
公开(公告)号：US4293819A
公开(公告)日：1981-10-06
申请号：US76428
申请日：1979-09-17
申请人： Akinori Shibayama , Kenji Maio , Norio Yokozawa
发明人： Akinori Shibayama , Kenji Maio , Norio Yokozawa
IPC分类号： H03F3/34 , H03F1/30 , H03F3/45 , H03F1/02
CPC分类号： H03F3/45479 , H03F1/30
摘要： A high-speed low-drift operational amplifier is disclosed in which a coefficient circuit having a voltage gain of more than 1 is formed employing a low frequency operational amplifier with a low-drift characteristic to multiply an input voltage by the voltage gain, the coefficient circuit and a low pass filter are connected in cascade to form a drift compensating circuit, and the inverting and non-inverting input terminals of a wide-band operational amplifier are connected to the input and output terminals of the drift compensating circuit, respectively.
摘要翻译：公开了一种高速低漂移运算放大器，其中使用具有低漂移特性的低频运算放大器形成具有大于1的电压增益的系数电路，以将输入电压乘以电压增益，系数电路和低通滤波器级联连接形成漂移补偿电路，宽带运算放大器的反相和非反相输入端分别连接到漂移补偿电路的输入和输出端。

7. 发明授权

US4449180A Sequence program inputting device 失效
标题翻译：顺序程序输入装置
公开(公告)号：US4449180A
公开(公告)日：1984-05-15
申请号：US374870
申请日：1982-05-04
申请人： Yoshimitsu Ohshima , Norio Yokozawa , Masayoshi Ohzeki
发明人： Yoshimitsu Ohshima , Norio Yokozawa , Masayoshi Ohzeki
IPC分类号： G06F3/02 , G05B19/00 , G05B19/05 , G06F9/06 , G06F17/50 , G06F15/46 , G06F9/00
CPC分类号： G05B19/056 , G05B2219/13018 , G05B2219/13048
摘要： A sequence program inputting device in a programmable sequence controller includes a separate producing circuit for producing a ladder diagram to be displayed on a display screen and a separate converting circuit for converting the ladder diagram to a machine instruction sequence of the programmable sequence controller to enable independent operations of those circuits.
摘要翻译：可编程顺序控制器中的顺序程序输入装置包括一个单独的产生电路，用于产生要显示在显示屏幕上的梯形图，以及单独的转换电路，用于将梯形图转换为可编程序控制器的机器指令序列，以使独立这些电路的操作。

8. 发明授权

US4106100A Digital differential analyzer 失效
标题翻译：数字差分分析仪
公开(公告)号：US4106100A
公开(公告)日：1978-08-08
申请号：US780457
申请日：1977-03-23
申请人： Kunihiro Okada , Yoshiharu Itatsuda , Takeyuki Endoh , Shigeru Yabuuchi , Norio Yokozawa
发明人： Kunihiro Okada , Yoshiharu Itatsuda , Takeyuki Endoh , Shigeru Yabuuchi , Norio Yokozawa
IPC分类号： G06F7/64 , G01N21/27 , G06F17/13 , G06J1/02 , G06F7/38
CPC分类号： G06F17/13 , G01N21/272
摘要： A digital differential analyzer comprises an arithmetic unit for performing an integration operation, a control unit for controlling the arithmetic unit, a plurality of temporary storage means in the arithmetic unit for temporarily storing interim results of the arithmetic operation therein to relieve the influence of propagation delay time of the arithmetic unit.
摘要翻译：数字差分分析仪包括用于执行积分运算的运算单元，用于控制算术单元的控制单元，用于临时存储算术运算中期结果的算术单元中的多个临时存储装置，以减轻传播延迟的影响算术单位的时间。

9. 发明授权

US5318034A Electrically adjustable delay circuit and ultrasonic diagnosis apparatus 失效
标题翻译：电动调节延时电路及超声波诊断仪
公开(公告)号：US5318034A
公开(公告)日：1994-06-07
申请号：US982558
申请日：1992-11-27
申请人： Kazunari Ishida , Kazutaka Okada , Toshio Kondo , Toshio Ogawa , Norio Yokozawa , Takashi Ichikawa
发明人： Kazunari Ishida , Kazutaka Okada , Toshio Kondo , Toshio Ogawa , Norio Yokozawa , Takashi Ichikawa
IPC分类号： G01S7/52 , A61B8/00
CPC分类号： G01S7/52046
摘要： This invention provides a delay circuit capable of electrically varying the delay amount comprising a first transistor for receiving a signal to be delayed from the base connected to an input terminal and outputting a positive phase signal and a negative phase signal with respect to the signal from the input terminal, respectively from the emitter and the collector thereof; two variable capacity diodes with their terminals of the same polarity connected together and a specified control voltage applied to the point of said connection, one end of the connected diodes being connected to the emitter of said first transistor; a second transistor with the base grounded, the emitter connected to the collector of the above-mentioned first transistor, and the collector connected to one end of a specified resistance; and a delayed signal output terminal having connected thereto the other end of the two variable capacity diodes and the other end of the specified resistance. According to this invention, an ultrasonic diagnosis apparatus using this delay circuit is also provided.
摘要翻译：本发明提供一种延迟电路，其能够电延迟量，包括第一晶体管，用于接收从连接到输入端子的基极延迟的信号，并输出正相信号和负相位信号分别从发射极和集电极输出端子; 两个具有相同极性的端子的可变容量二极管连接在一起，并且将指定的控制电压施加到所述连接点，所连接的二极管的一端连接到所述第一晶体管的发射极; 第二晶体管，其基极接地，发射极连接到上述第一晶体管的集电极，并且集电极连接到指定电阻的一端; 以及延迟信号输出端子，其连接到两个可变容量二极管的另一端和指定电阻的另一端。根据本发明，还提供了使用该延迟电路的超声波诊断装置。

10. 发明授权

US4316178A Digital-to-analog conversion system with compensation circuit 失效
标题翻译：具有补偿电路的数模转换系统
公开(公告)号：US4316178A
公开(公告)日：1982-02-16
申请号：US113674
申请日：1980-01-21
申请人： Akinori Shibayama , Kenji Maio , Masao Hotta , Norio Yokozawa
发明人： Akinori Shibayama , Kenji Maio , Masao Hotta , Norio Yokozawa
IPC分类号： H03M1/10 , H03M1/00 , H03K13/02
CPC分类号： H03M1/1071 , H03M1/74
摘要： In a digital-to-analog converter having means to convert a digital input signal into an analog signal, processing means to evaluate an error attendant upon the conversion, and memory means to store the evaluated error; a digital-to-analog converter with a compensating circuit wherein the processing means comprises a ramp voltage generator, a clock pulse generator, and counting means to count clock pulses of the generator and to deliver the error on the basis of the count value of the clock pulses at each time when the ramp voltage exceeds the output of the conversion means.
摘要翻译：在具有将数字输入信号转换为模拟信号的装置的数模转换器中，用于评估转换时伴随的误差的处理装置以及存储评估误差的存储装置; 具有补偿电路的数模转换器，其中所述处理装置包括斜坡电压发生器，时钟脉冲发生器和计数装置，用于对所述发生器的时钟脉冲进行计数，并基于所述发生器的计数值来递送所述误差当斜坡电压超过转换装置的输出时，每个时钟脉冲。

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