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1. 发明授权

US5770495A Method of fabricating semiconductor device including high temperature heat treatment 失效
标题翻译：制造包括高温热处理的半导体器件的方法
公开(公告)号：US5770495A
公开(公告)日：1998-06-23
申请号：US548913
申请日：1995-10-26
申请人： Nolifumi Sato , Shinji Ohara , Hitoshi Mitani , Hidetaka Natsume , Takami Hiruma
发明人： Nolifumi Sato , Shinji Ohara , Hitoshi Mitani , Hidetaka Natsume , Takami Hiruma
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8234 , H01L21/8247 , H01L23/52 , H01L23/522 , H01L27/088 , H01L29/786 , H01L29/788 , H01L29/792 , H01L21/283 , H01L21/8244
CPC分类号： H01L21/28518
摘要： The invention provides a method of fabricating a semiconductor device, including the steps of (a) forming an impurity region at a surface of a silicon substrate, (b) depositing an insulative film over the silicon substrate, (c) forming a contact hole through the insulative film to expose the impurity region of the silicon substrate, (d) forming an electrode wiring over the contact hole, the electrode wiring comprising a refractory metal silicide film and a silicon film overlying on the metal silicide film, the metal silicide film overlying the exposed impurity region, (e) depositing a second insulative film over a resultant, (f) depositing a polysilicon film on the second insulative film, (g) patterning the polysilicon film to form an element, and (h) heat-treating a resultant at high temperature in oxidizing atmosphere. The step (h) is to be carried out at any time after the step (f) has been completed. In the method, even if a semiconductor device is heat-treated at high temperature in oxidizing atmosphere, there occurs no voids in the silicon substrate below the refractory metal silicide film. This is because silicon atoms are supplied from the silicon film overlying on the refractory metal silicide film to the metal silicide film. Thus, reliable electrical connection between the electrode wiring and the silicon substrate is ensured.
摘要翻译：本发明提供一种制造半导体器件的方法，包括以下步骤：（a）在硅衬底的表面形成杂质区，（b）在硅衬底上沉积绝缘膜，（c）形成接触孔所述绝缘膜暴露所述硅衬底的杂质区域，（d）在所述接触孔上形成电极布线，所述电极布线包括难熔金属硅化物膜和覆盖在所述金属硅化物膜上的硅膜，所述金属硅化物膜覆盖暴露的杂质区域，（e）在结果上沉积第二绝缘膜，（f）在第二绝缘膜上沉积多晶硅膜，（g）图案化多晶硅膜以形成元件，和（h）热处理在高温氧化气氛中产生。步骤（h）将在步骤（f）完成后的任何时间进行。在该方法中，即使半导体器件在氧化气氛中在高温下进行热处理，硅基底中的难熔金属硅化物膜下面也不会发生空隙。这是因为硅原子从覆盖在难熔金属硅化物膜上的硅膜供应到金属硅化物膜。因此，确保电极布线和硅基板之间的可靠的电连接。

2. 发明授权

US5761113A Soft error suppressing resistance load type SRAM cell 失效
标题翻译：软误差抑制电阻负载型SRAM单元
公开(公告)号：US5761113A
公开(公告)日：1998-06-02
申请号：US550348
申请日：1995-10-30
申请人： Hidetaka Natsume , Nolifumi Sato , Hitoshi Mitani , Takami Hiruma
发明人： Hidetaka Natsume , Nolifumi Sato , Hitoshi Mitani , Takami Hiruma
IPC分类号： H01L27/10 , G11C11/412 , G11C11/00
CPC分类号： G11C11/4125
摘要： In an SRAM cell including two cross-coupled inverters each having a first resistance element and a drive MOS transistor, a second resistance element is connected between the first and the drive MOS transistor. A gate electrode of the drive MOS transistor of one of the inverters is connected between the first and second resistance elements of the other.
摘要翻译：在包括两个具有第一电阻元件和驱动MOS晶体管的交叉耦合反相器的SRAM单元中，第二电阻元件连接在第一驱动MOS晶体管和驱动MOS晶体管之间。其中一个逆变器的驱动MOS晶体管的栅电极连接在第一和第二电阻元件之间。

3. 发明授权

US6031291A Common contact hole structure in semiconductor device 失效
标题翻译：半导体器件中常见的接触孔结构
公开(公告)号：US6031291A
公开(公告)日：2000-02-29
申请号：US550159
申请日：1995-10-30
申请人： Norifumi Sato , Takami Hiruma , Hitoshi Mitani , Hidetaka Natsume
发明人： Norifumi Sato , Takami Hiruma , Hitoshi Mitani , Hidetaka Natsume
IPC分类号： H01L27/11 , H01L21/28 , H01L21/8244 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/0276 , H01L21/76816 , H01L27/11 , H01L27/1112
摘要： A semiconductor device having a semiconductor substrate, an impurity diffused layer formed in a principal surface of the semiconductor substrate, a conductive member formed on the semiconductor substrate adjacent to the impurity diffused layer and having a sloped surface inclined to the principal surface of the semiconductor substrate, an insulator film deposited to cover the impurity diffused layer and the conductive member, and a common contact hole formed through the insulator film to extend over a surface of the impurity diffused layer and the sloped surface of the conductive member.
摘要翻译：一种具有半导体衬底的半导体器件，形成在半导体衬底的主表面上的杂质扩散层，形成在与半导体衬底相邻的杂质扩散层上并具有倾斜表面的半导体衬底的主表面的导电部件沉积以覆盖杂质扩散层和导电构件的绝缘膜，以及通过绝缘膜形成的公共接触孔，以在杂质扩散层的表面和导电构件的倾斜表面上延伸。

4. 发明授权

US5721619A Misregistration detecting marks for pattern formed on semiconductor substrate 失效
标题翻译：在半导体衬底上形成图案的对准检测标记
公开(公告)号：US5721619A
公开(公告)日：1998-02-24
申请号：US767846
申请日：1996-12-17
申请人： Takami Hiruma , Norifumi Sato
发明人： Takami Hiruma , Norifumi Sato
IPC分类号： G03F1/42 , G03F7/20 , H01L21/027 , G01B11/00
CPC分类号： G03F7/70633
摘要： A semiconductor device according to the present invention has misregistration detecting marks provided in the periphery of a semiconductor chip. The misregistration detecting marks consist of a first scale mark for detecting misalignment in a first direction, a second scale mark for detecting misalignment in a second direction perpendicular to the first direction, and a third scale mark for detecting misalignment in a third direction making respectively specified angles with the first direction and the second direction.
摘要翻译：根据本发明的半导体器件具有设置在半导体芯片周围的不对准检测标记。不对准检测标记包括用于检测在第一方向上的不对准的第一刻度标记，用于检测与第一方向垂直的第二方向上的未对准的第二刻度标记和用于检测分别指定的第三方向上的未对准的第三刻度标记与第一方向和第二方向成角度。

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