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1. 发明授权

US06291347B1 Method and system for constructing semiconductor devices 有权
标题翻译：构造半导体器件的方法和系统
公开(公告)号：US06291347B1
公开(公告)日：2001-09-18
申请号：US09671328
申请日：2000-09-26
申请人： Noel M. Russell , Anthony J. Konecni
发明人： Noel M. Russell , Anthony J. Konecni
IPC分类号： H01L2144
CPC分类号： C23C16/45597 , C23C16/18 , C23C16/4401 , C23C16/45591 , H01L21/28556
摘要： A system for constructing semiconductor devices is disclosed. The system comprises a wafer (102) having semiconductor devices (104), a bevel (108), an edge (110), a frontside (111), and a backside (112). The system also has a chamber (107), and a heater (106) coupled to the interior of the chamber (107) and operable to hold and heat the wafer (102). A showerhead (114) is also coupled to the interior of the chamber (107) and is operable to introduce a precursor gas (116) containing copper over the wafer (102). A shield (118) is coupled to the interior of the chamber (107) and is operable to partially shield the bevel (108), the edge (110), and the backside (112) of the wafer (102) from the precursor gas (116). There is an opening (122) in the chamber (107) through which a reactive backside gas (124) may be introduced under the wafer (102). A method for constructing semiconductor devices is disclosed. Step one calls for placing a wafer (102) on a heater (106) in a chamber (107). Step two requires heating the wafer with a heater (106). Step three provides for partially shielding the wafer (102) with a shield (118). In step four, the method provides for introducing a precursor gas (116) containing copper into the chamber (107) above the wafer (102). The last step calls for introducing a reactive backside gas (124) into the chamber (107) below the wafer (102) through an opening (122).
摘要翻译：公开了一种用于构造半导体器件的系统。该系统包括具有半导体器件（104），斜面（108），边缘（110），前侧（111）和背面（112）的晶片（102）。该系统还具有室（107）和联接到室（107）的内部并且可操作以保持和加热晶片（102）的加热器（106）。淋浴头（114）也联接到腔室（107）的内部，并且可操作以将含有铜的前体气体（116）引入晶片（102）上。屏蔽件（118）联接到腔室（107）的内部并且可操作以将晶片（102）的斜面（108），边缘（110）和背面（112）部分地从前体气体（116）。在腔室（107）中有一个开口（122），反应性后侧气体（124）可以通过该开口引入晶片（102）下面。公开了一种用于构造半导体器件的方法。步骤一要求将晶片（102）放置在室（107）中的加热器（106）上。第二步需要用加热器（106）加热晶片。步骤三提供了用屏蔽件（118）部分地屏蔽晶片（102）。在步骤四中，该方法提供了将含有铜的前体气体（116）引入晶片（102）上方的室（107）中。最后一步要求通过开口（122）将反应后侧气体（124）引入晶片（102）下方的室（107）中。

2. 发明授权

US06455419B1 System and method of forming a tungsten plug 有权
标题翻译：形成钨丝塞的系统和方法
公开(公告)号：US06455419B1
公开(公告)日：2002-09-24
申请号：US09392274
申请日：1999-09-09
申请人： Anthony J. Konecni , Srikanth Bolnedi
发明人： Anthony J. Konecni , Srikanth Bolnedi
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76856 , H01L21/76862 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).
摘要翻译：提供一种电子装置，其损害从衬底（10）向外设置的电介质层（12）。电介质层（12）具有通过介电层（12）形成的至少一个接触开口（14）。该器件具有从电介质层（12）和衬底（10）的暴露表面向外设置的粘附层（16）。第一阻挡层（18）从粘合层（16）向外形成。第二阻挡层（20）从第一阻挡层（18）向外形成。导电插头（24）填充接触开口（14）并且设置在第二阻挡层（20）的外侧。

3. 发明授权

US06215186B1 System and method of forming a tungstein plug 有权
标题翻译：形成钨丝塞的系统和方法
公开(公告)号：US06215186B1
公开(公告)日：2001-04-10
申请号：US09225576
申请日：1999-01-05
申请人： Anthony J. Konecni , Srikanth Bolnedi
发明人： Anthony J. Konecni , Srikanth Bolnedi
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76856 , H01L21/76862 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).
摘要翻译：提供一种电子装置，其损害从衬底（10）向外设置的电介质层（12）。电介质层（12）具有通过介电层（12）形成的至少一个接触开口（14）。该器件具有从电介质层（12）和衬底（10）的暴露表面向外设置的粘附层（16）。第一阻挡层（18）从粘合层（16）向外形成。第二阻挡层（20）从第一阻挡层（18）向外形成。导电插头（24）填充接触开口（14）并且设置在第二阻挡层（20）的外侧。

4. 发明授权

US6069072A CVD tin barrier layer for reduced electromigration of aluminum plugs 失效
标题翻译： CVD锡阻隔层，用于减少铝塞的电迁移
公开(公告)号：US6069072A
公开(公告)日：2000-05-30
申请号：US060920
申请日：1998-04-15
申请人： Anthony J. Konecni , Girish Anant Dixit
发明人： Anthony J. Konecni , Girish Anant Dixit
IPC分类号： C23C16/20 , C23C16/34 , H01L21/285 , H01L21/768 , H01L21/4763
CPC分类号： C23C16/20 , C23C16/34 , H01L21/32051 , H01L21/76841 , H01L23/53223 , H01L2924/0002
摘要： A structure and method incorporating a CVD TiN barrier layer 230 over the aluminum plug 220 in order to prevent the high plug resistance caused by the blanket metal film stack 240, 250, and 260 deposition process. Unlike physical vapor deposited (PVD) TiN, CVD TiN 230 does not react with the aluminum 220 during annealing. CVD TiN has also been shown to be a better diffusion barrier for aluminum than PVD TiN. In addition, CVD TiN will disrupt any unfavorable grain boundary propagation through the aluminum plug which may act as a source of electromigration failure. Therefore, the CVD TiN 230 can increase the electromigration resistance, without increasing the contact/via resistance.
摘要翻译：为了防止由覆盖金属膜叠层240,250和260沉积过程引起的高插塞电阻，在铝插头220上结合有CVD TiN阻挡层230的结构和方法。与物理气相沉积（PVD）TiN不同，CVD TiN 230在退火过程中不与铝220反应。 CVD TiN也被证明是比PVD TiN更好的铝扩散阻挡层。此外，CVD TiN将破坏可能作为电迁移故障源的铝塞的任何不利的晶界传播。因此，CVD TiN 230可以增加电迁移电阻，而不增加接触/通孔电阻。

5. 发明授权

US06660650B1 Selective aluminum plug formation and etchback process 有权
标题翻译：选择性铝塞形成和回蚀工艺
公开(公告)号：US06660650B1
公开(公告)日：2003-12-09
申请号：US09467108
申请日：1999-12-17
申请人： Anthony J. Konecni , Wei-yung Hsu , Qi-zhong Hong
发明人： Anthony J. Konecni , Wei-yung Hsu , Qi-zhong Hong
IPC分类号： H01L2100
CPC分类号： H01L21/7684 , H01L21/76879 , H01L21/76895 , H01L28/60
摘要： An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate having an interconnecting structure comprised of aluminum, the method comprising the steps of: forming a conductive structure (layers 120, 122 and 128 of FIGS. 1a-1d) comprised of a metal; forming a dielectric layer (layer 130 of FIGS. 1a-1d) over the conductive structure, the dielectric layer having an upper surface; forming an opening in the dielectric layer so as to expose a portion of the conductive structure, the opening having sidewalls; selectively depositing an aluminum-containing conductive material (material 136 and 137 of FIG. 1c) in the opening; and performing an etchback process so as to remove any of the aluminum-containing conductive material formed on the hardmask and so as to etchback any portion of the aluminum-containing conductor which is situated over the upper surface of the dielectric layer. In an alternative embodiment, the method further comprises the step of: forming a hardmask on the upper surface of the dielectric layer, the hardmask having an upper surface and is formed prior to the step of forming an opening in the dielectric layer; and wherein an opening is formed in the hardmask prior to the step of forming an opening in the dielectric layer.
摘要翻译：本发明的一个实施例是一种在具有由铝构成的互连结构的半导体衬底上制造电子器件的方法，该方法包括以下步骤：形成导电结构（图1a-1d的层120,122和128））由金属组成; 在所述导电结构上形成介电层（图1a-1d的层130），所述电介质层具有上表面; 在所述电介质层中形成开口以暴露所述导电结构的一部分，所述开口具有侧壁; 选择性地将铝的导电材料（图1c的材料136和137）沉积在开口中; 并且执行回蚀处理，以便去除形成在硬掩模上的任何含铝导电材料，并且回蚀位于介电层上表面上方的含铝导体的任何部分。在替代实施例中，该方法还包括以下步骤：在电介质层的上表面上形成硬掩模，硬掩模具有上表面，并且在形成介质层中的开口的步骤之前形成; 并且其中在形成所述电介质层中的开口的步骤之前，在所述硬掩模中形成开口。

6. 发明授权

US5981382A PVD deposition process for CVD aluminum liner processing 失效
标题翻译： CVD铝衬里加工的PVD沉积工艺
公开(公告)号：US5981382A
公开(公告)日：1999-11-09
申请号：US42199
申请日：1998-03-13
申请人： Anthony J. Konecni , Noel Russell
发明人： Anthony J. Konecni , Noel Russell
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76876 , H01L21/76843 , H01L21/76877
摘要： An embodiment of the instant invention is a method of fabricating a conductive structure for electrically connecting one portion of a semiconductor device to another portion of the device, the method comprising the steps of: providing a continuous liner layer (step 104) of the semiconductor substrate, the liner layer comprised of CVD Al; forming a first conductor (step 106) on the liner layer, the first conductor formed using a source whose output power is in the range of 1 to 5 kW; and forming a second conductor (step 108) on the first conductor, the second conductor formed using a source whose output power is in the range of 10 to 20 kW. Preferably, the conductive structure is selected from the group consisting of: contact, via, and trench. In an alternative embodiment, a nucleation layer is formed (step 104) beneath the continuous liner layer. The nucleation layer is, preferably, comprised of titanium or a Ti/TiN stack. Preferably, the step of forming a first conductor on the liner layer is comprised of depositing an aluminum containing layer using physical vapor deposition. In addition, the step of forming a second conductor on the first conductor is, preferably, comprised of depositing an aluminum containing layer using physical vapor deposition.
摘要翻译：本发明的一个实施例是制造用于将半导体器件的一部分电连接到器件的另一部分的导电结构的方法，所述方法包括以下步骤：提供半导体衬底的连续衬层（步骤104）由CVD Al构成的衬层; 在所述衬垫层上形成第一导体（步骤106），所述第一导体使用输出功率在1至5kW范围内的源形成; 以及在所述第一导体上形成第二导体（步骤108），所述第二导体使用输出功率在10至20kW范围内的源形成。优选地，导电结构选自：接触，通孔和沟槽。在替代实施例中，在连续衬层下方形成成核层（步骤104）。成核层优选由钛或Ti / TiN叠层组成。优选地，在衬层上形成第一导体的步骤包括使用物理气相沉积沉积含铝层。此外，在第一导体上形成第二导体的步骤优选地包括使用物理气相沉积沉积含铝层。

7. 发明授权

US5849367A Elemental titanium-free liner and fabrication process for inter-metal connections 失效
标题翻译：元素无钛衬里和金属间连接的制造工艺
公开(公告)号：US5849367A
公开(公告)日：1998-12-15
申请号：US764674
申请日：1996-12-11
申请人： Girish A. Dixit , Anthony J. Konecni
发明人： Girish A. Dixit , Anthony J. Konecni
IPC分类号： C23C14/02 , H01L21/768
CPC分类号： H01L21/76846 , C23C14/022 , H01L21/76814 , H01L21/76843 , H01L21/76862 , H01L21/76877
摘要： An elemental titanium-free liner and cavity cleansing process is provided that allows for the elimination of conventional sputter etch and elemental titanium depositions. A low power plasma etch provides for pre-conditioning/cleansing of cavities such as contacts and vias. A refractory metal is provided as a cavity liner. Preferably, the liner is comprised of several discrete refractory metal liner layers, each having a thickness of about 25-100 .ANG., that can be applied by CVD and/or PVD. A low power plasma cleanse is preferably interposed between each liner layer deposition. A suitable metal plug can be deposited and directed into the cavity to complete cavity filling. Preferably, the metal plug is an elemental aluminum or aluminum alloy plug that is deposited by CVD and force-filled into the cavity to reduce the incidence of micro-voids within the cavity. Elimination of the conventional sputter etch and the high temperature processing (temp..gtoreq..sup..about. 400.degree. C.) associated with such processing allows for the use of polymeric dielectrics, such as the family of polytetrafluorethylene ("PTFE") compounds, which exhibit a dielectric constant (.kappa.) of about 1.9; parylene (.kappa.=.sup..about. 2.2-2.6); aerogels and xerogels (.kappa.=.sup..about. 1.1-1.8); and the family of polymeric spin-on-glass ("SOG") materials; use of all the foregoing materials being attractive because of the ability of these materials to reduce parasitic capacitance of the interconnects. Because these polymeric materials are temperature sensitive, their use has been limited, as conventional device fabrication practices typically require operation temperatures far in excess of the melting and/or decomposition temperature for these materials.
摘要翻译：提供了元素无钛衬里和空腔清洁工艺，其允许消除常规的溅射蚀刻和元素钛沉积。低功率等离子体蚀刻提供诸如触点和通孔之类的空腔的预调节/清洁。提供难熔金属作为空腔衬垫。优选地，衬套由几个分立的难熔金属衬垫层组成，每层具有约25-100的厚度，可以通过CVD和/或PVD施加。优选地，在每个衬垫层沉积之间插入低功率等离子体清洁。可以将合适的金属塞子沉积并引导到空腔中以完成空腔填充。优选地，金属插塞是元素铝或铝合金插塞，其通过CVD沉积并强力填充到空腔中以减少空腔内的微孔的入射。消除常规的溅射蚀刻和与这种处理相关的高温处理（温度> = = DIFFERENCE 400℃）允许使用聚合物电介质，例如聚四氟乙烯（“PTFE”）族化合物，其表现出介电常数（kappa）约为1.9; 聚对二甲苯（kappa = DIFFERENCE 2.2-2.6）; 气凝胶和干凝胶（kappa = DIFFERENCE 1.1-1.8）; 和聚合物旋涂玻璃（“SOG”）材料的家族; 使用所有上述材料是有吸引力的，因为这些材料能够减少互连的寄生电容。由于这些聚合物材料是温度敏感的，因此其使用受到限制，因为传统的器件制造实践通常需要远远超过这些材料的熔化和/或分解温度的操作温度。

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