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1. 发明申请

US20070243684A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFATURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070243684A1
公开(公告)日：2007-10-18
申请号：US11767074
申请日：2007-06-22
申请人： Nobuyuki KATSUKI , Atsushi OGA , Shuuichi SENOU , Noriyuki OTA , Masahiro YOSHIDA , Kenta ARAI , Atsushi NAKAGAWA , Tomotaka MURAKAMI
发明人： Nobuyuki KATSUKI , Atsushi OGA , Shuuichi SENOU , Noriyuki OTA , Masahiro YOSHIDA , Kenta ARAI , Atsushi NAKAGAWA , Tomotaka MURAKAMI
IPC分类号： H01L21/8234
CPC分类号： H01L27/088 , H01L21/823412 , H01L29/1045
摘要： The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.
摘要翻译：半导体器件包括参考电压发生器电路和与参考电压发生器电路不同的电路。参考电压发生器电路的半导体元件具有至少在漏极区附近衬底杂质浓度基本均匀的沟道区。与参考电压发生器电路不同的电路的半导体元件具有至少在漏极区域中衬底杂质浓度高于该区域的其它部分的沟道区域。

2. 发明申请

US20080191990A1 DRIVER AND DISPLAY METHOD USING THE SAME 审中-公开
标题翻译：使用它的驱动器和显示方法
公开(公告)号：US20080191990A1
公开(公告)日：2008-08-14
申请号：US12026613
申请日：2008-02-06
申请人： Hiroyuki MATSUBARA , Hiroyuki TAKAHASHI , Nobuyuki ORITA , Toshiharu OKAMOTO , Shuuichi SENOU
发明人： Hiroyuki MATSUBARA , Hiroyuki TAKAHASHI , Nobuyuki ORITA , Toshiharu OKAMOTO , Shuuichi SENOU
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G09G3/3685 , G09G2310/0275 , G09G2330/08
摘要： A driver includes a first memory including a plurality of memory cells and redundant memory cells. An address control circuit replaces a defective memory cell of the plurality of memory cells with one of the redundant memory cells based on a defect address data indicating an address of the defective memory cell. A driving circuit displays on a display panel, a display data stored in the first memory based on a display quality specifying data specifying display quality of the display panel. The display quality specifying data and the defect address data are stored in a second memory.
摘要翻译：驱动器包括包括多个存储单元和冗余存储单元的第一存储器。地址控制电路基于指示有缺陷的存储单元的地址的缺陷地址数据，用冗余存储单元之一代替多个存储单元的有缺陷的存储单元。基于指定显示面板的显示质量的显示质量指定数据，驱动电路在显示面板上显示存储在第一存储器中的显示数据。显示质量指定数据和缺陷地址数据被存储在第二存储器中。

3. 发明申请

US20130058173A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130058173A1
公开(公告)日：2013-03-07
申请号：US13607306
申请日：2012-09-07
申请人： Shuuichi SENOU , Kenjyu Shimogawa , Susumu Takano , Toshihiko Funaki , Hideaki Arima
发明人： Shuuichi SENOU , Kenjyu Shimogawa , Susumu Takano , Toshihiko Funaki , Hideaki Arima
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G06F3/0635 , G06F13/4022
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，存储第一和第二模式信息的模式信息存储单元，能够通过第一总线接口设置的第一和第二模式信息电路，基于第一模式信息操作的第一存储器核心，第一存储器核心连接到第一总线接口电路并被提供有第一时钟信号，第二存储器内核，第二存储器核心被提供有第二存储器核心时钟信号和选择电路，其基于预定的切换信息选择性地将第二存储器核心连接到第一或第二总线接口电路，其中当第二存储器核心连接到第二存储器核心时，第二存储器核心基于第二模式信息操作第二总线接口电路。

4. 发明申请

US20130051110A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130051110A1
公开(公告)日：2013-02-28
申请号：US13599730
申请日：2012-08-30
申请人： Toshihiko FUNAKI , Toshiharu OKAMOTO , Muneaki MATSUSHIGE , Kenichi KUBOYAMA , Shuuichi SENOU , Susumu TAKANO
发明人： Toshihiko FUNAKI , Toshiharu OKAMOTO , Muneaki MATSUSHIGE , Kenichi KUBOYAMA , Shuuichi SENOU , Susumu TAKANO
IPC分类号： G11C5/06
CPC分类号： G11C7/1048 , G11C7/00 , G11C7/10 , G11C7/1006 , G11C8/12 , G11C11/4096 , H03K5/15006
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，通过第一数据总线连接到第一总线接口电路的第一存储器核心，第一存储器核心连接到第一存取控制信号从第一总线接口电路输出的第二存储器核心，通过第二数据总线连接到第二总线接口电路的第二存储器核心，以及选择性地将第一存取控制信号和第二存取控制信号输出的第二存取控制信号第二总线接口电路到第二存储器核心。

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