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1. 发明授权

US06372593B1 Method of manufacturing SOI substrate and semiconductor device 失效
标题翻译：制造SOI衬底和半导体器件的方法
公开(公告)号：US06372593B1
公开(公告)日：2002-04-16
申请号：US09619579
申请日：2000-07-19
申请人： Nobuyoshi Hattori , Satoshi Yamakawa , Junji Nakanishi
发明人： Nobuyoshi Hattori , Satoshi Yamakawa , Junji Nakanishi
IPC分类号： H01L21331
CPC分类号： H01L21/76256 , H01L27/10873 , H01L27/1203 , Y10S438/933
摘要： First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.
摘要翻译：首先，通过外延在接合晶片的主表面上形成硅锗单晶层和硅单晶层。接合晶片的整个表面被氧化以形成氧化硅层。然后，将基底晶片接合到接合晶片。将接合晶片和彼此接合的基底晶片加热，以加强它们之间的粘合。然后，通过用氯气等离子体蚀刻除去接合晶片，同时使硅锗单晶层用作止动器。此后，通过化学机械抛光对硅锗单晶层进行抛光，以具有适于形成器件的厚度。这样实现的是通过接合制造SOI衬底的方法，该SOI衬底可以采用具有小的不规则性的晶体状态的层作为具有对单晶硅的选择性的阻挡层，并且有效地使用该阻挡件作为器件形成层。

2. 发明授权

US06465316B2 SOI substrate and semiconductor device 失效
标题翻译： SOI衬底和半导体器件
公开(公告)号：US06465316B2
公开(公告)日：2002-10-15
申请号：US09975977
申请日：2001-10-15
申请人： Nobuyoshi Hattori , Satoshi Yamakawa , Junji Nakanishi
发明人： Nobuyoshi Hattori , Satoshi Yamakawa , Junji Nakanishi
IPC分类号： H01L21331
CPC分类号： H01L21/76256 , H01L27/10873 , H01L27/1203 , Y10S438/933
摘要： First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.
摘要翻译：首先，通过外延在接合晶片的主表面上形成硅锗单晶层和硅单晶层。接合晶片的整个表面被氧化以形成氧化硅层。然后，将基底晶片接合到接合晶片。将接合晶片和彼此接合的基底晶片加热，以加强它们之间的粘合。然后，通过用氯气等离子体蚀刻除去接合晶片，同时使硅锗单晶层用作止动器。此后，通过化学机械抛光对硅锗单晶层进行抛光，以具有适于形成器件的厚度。这样实现的是通过接合制造SOI衬底的方法，该SOI衬底可以采用具有小的不规则性的晶体状态的层作为具有对单晶硅的选择性的阻挡层，并且有效地使用该阻挡件作为器件形成层。

3. 发明授权

US06252294B1 Semiconductor device and semiconductor storage device 失效
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US06252294B1
公开(公告)日：2001-06-26
申请号：US09438578
申请日：1999-11-12
申请人： Nobuyoshi Hattori , Hideki Naruoka , Hidekazu Yamamoto
发明人： Nobuyoshi Hattori , Hideki Naruoka , Hidekazu Yamamoto
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L23/26 , H01L27/1203 , H01L2924/0002 , Y10S257/903 , Y10S257/913 , H01L2924/00
摘要： A semiconductor device and a semiconductor storage device having an SOI structure and being enable sufficient gettering performance without imposing limitations on the freedom of design of an LSI circuit. A semiconductor device includes a semiconductor wafer of SOI structure which has a insulation layer and a silicon layer provided thereon, wherein the semiconductor wafer includes a plurality of element fabrication regions where semiconductor elements are fabricated, and a cutting region provided between the element fabrication regions. Gettering sites are formed in the cutting region by means of embedding a gettering member into grooves of predetermined depth.
摘要翻译：具有SOI结构的半导体器件和半导体存储器件，并且能够实现充分的吸杂性能，而不会对LSI电路的设计自由度施加限制。半导体器件包括SOI结构的半导体晶片，其具有绝缘层和设置在其上的硅层，其中半导体晶片包括多个制造半导体元件的元件制造区域和设置在元件制造区域之间的切割区域。通过将吸气构件嵌入到预定深度的凹槽中，在切割区域中形成吸气部位。

4. 发明授权

US6016562A Inspection data analyzing apparatus for in-line inspection with enhanced display of inspection results 失效
标题翻译：检查数据分析仪器，用于在线检测，增强了检测结果的显示
公开(公告)号：US6016562A
公开(公告)日：2000-01-18
申请号：US919166
申请日：1997-08-28
申请人： Yoko Miyazaki , Nobuyoshi Hattori , Junko Izumitani , Masahiko Ikeno
发明人： Yoko Miyazaki , Nobuyoshi Hattori , Junko Izumitani , Masahiko Ikeno
IPC分类号： H01L21/66 , G01R31/01 , G01R31/28 , G06F11/10
CPC分类号： G01R31/01 , G01R31/2831 , H01L22/12
摘要： An ordinary user can easily learn a step at which a problem occurs during semiconductor manufacturing processes and improve the yield of manufacturing products and the quality of the products. At a certain in-line inspection step, a CPU (3) stores data signals (V1) taken by an inspection apparatus (1) into a memory (2), and reads a result (V6) obtained at a precedent step and stores the same in the memory (2). The CPU (3) reads stored data signals (V2) from the memory (2), performs comparison or referral on data about defects which are detected at a current step and the result (V6) regarding the precedent step, and generates a defect data analysis processing result signal (V5) regarding the current step. The result (V5) consists of disappeared defect data, common defect data, new defect data to which a label of a current step number is assigned, and reappeared defect data. The CPU (3) performs the processing above for each in-line inspection step, edits resultant data, and generates histogram data which provide the number of detected defects and the number of disappeared defects for each step.
摘要翻译：普通用户可以轻松地学习在半导体制造过程中发生问题的步骤，并提高制造产品的产量和产品的质量。在某个在线检查步骤中，CPU（3）将由检查装置（1）取得的数据信号（V1）存储到存储器（2）中，并读取在先前步骤获得的结果（V6）在内存中相同（2）。 CPU（3）从存储器（2）读取存储的数据信号（V2），对与当前步骤检测到的缺陷有关的数据和关于先前步骤的结果（V6）进行比较或推荐，生成缺陷数据关于当前步骤的分析处理结果信号（V5）。结果（V5）由消失的缺陷数据，公共缺陷数据，分配了当前步骤编号的标签的新缺陷数据和重新出现的缺陷数据组成。 CPU（3）对于每个在线检查步骤执行上述处理，编辑结果数据，并且生成提供检测到的缺陷数量和每个步骤的消失缺陷数量的直方图数据。

5. 发明授权

US08242605B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08242605B2
公开(公告)日：2012-08-14
申请号：US12795863
申请日：2010-06-08
申请人： Hiroyuki Arie , Nobuaki Umemura , Nobuyoshi Hattori , Nobuto Nakanishi , Kimio Hara , Kyoya Nitta , Makoto Ishikawa
发明人： Hiroyuki Arie , Nobuaki Umemura , Nobuyoshi Hattori , Nobuto Nakanishi , Kimio Hara , Kyoya Nitta , Makoto Ishikawa
IPC分类号： H01L23/48
CPC分类号： H01L29/7835 , H01L21/02057 , H01L21/743 , H01L29/4175 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
摘要翻译：在具有LDMOSFET的半导体器件中，源电极位于其后表面。因此，为了降低顶表面的源极接触区域与后表面的源电极之间的电阻，提供了通过P型外延从上表面延伸到P +型衬底的多晶硅埋入式插塞并用硼重掺杂。在多晶硅埋塞塞周围的单晶硅区域发生位错，引起泄漏故障。半导体器件具有延伸穿过具有不同杂质浓度的第一和第二半导体层之间的边界表面的硅基插塞。至少插头的内部是多晶区域。在多晶区域的表面中，位于与其相邻的上述边界面的两侧的部分各自被固相外延区域覆盖。

6. 发明授权

US07674668B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07674668B2
公开(公告)日：2010-03-09
申请号：US12005444
申请日：2007-12-26
申请人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
发明人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.
摘要翻译：在半导体衬底的主表面上形成栅电极之后，通过使用栅电极作为掩模，在半导体衬底的主表面上注入杂质，形成低浓度层。此后，在栅电极的两个侧表面上形成第一侧壁和第二侧壁。随后，使用第一侧壁，第二侧壁和栅电极作为掩模，将氮等离子注入到半导体衬底中，从而在半导体衬底的主表面上形成结晶化控制区域（CCR）。然后，在去除第二侧壁之后，在半导体衬底的主表面上形成用于源极和漏极的高浓度层。

7. 发明授权

US06473665B2 Defect analysis method and process control method 失效
公开(公告)号：US06473665B2
公开(公告)日：2002-10-29
申请号：US09920818
申请日：2001-08-03
申请人： Toshiaki Mugibayashi , Nobuyoshi Hattori
发明人： Toshiaki Mugibayashi , Nobuyoshi Hattori
IPC分类号： G06F1900
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

8. 发明授权

US06341241B1 Defect analysis method and process control method 有权
标题翻译：缺陷分析方法和过程控制方法
公开(公告)号：US06341241B1
公开(公告)日：2002-01-22
申请号：US09206150
申请日：1998-12-07
申请人： Toshiaki Mugibayashi , Nobuyoshi Hattori
发明人： Toshiaki Mugibayashi , Nobuyoshi Hattori
IPC分类号： G06F1900
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.
摘要翻译：缺陷分析方法可以定量地掌握单个过程的新缺陷数量对器件产量的影响。在每个芯片中由于指定的处理而存在或不存在新缺陷之后，通过电测试器判断芯片的缺陷性或非缺陷性，将晶片上的多个芯片分为四组：{ 圆（1）}无缺陷芯片无新缺陷; {圈（2）}缺陷芯片没有新的缺陷; {圈（3）}无缺陷芯片新缺陷; 和{圈绕（4）}缺陷芯片有新的缺陷，以获得仅由指定过程的新缺陷引起的新的有缺陷的芯片的数量; 芯片被认为有缺陷的指定工艺的新缺陷的临界比率; 以及被认为是由指定处理引起的处理有缺陷的芯片的数量。

9. 发明授权

US06741940B2 Computer-implemented method of defect analysis 失效
标题翻译：计算机实现的缺陷分析方法
公开(公告)号：US06741940B2
公开(公告)日：2004-05-25
申请号：US10224469
申请日：2002-08-21
申请人： Toshiaki Mugibayashi , Nobuyoshi Hattori
发明人： Toshiaki Mugibayashi , Nobuyoshi Hattori
IPC分类号： G06F1900
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： In the step (S11), chip classification data in which a plurality of chips are classified into four sorts on the basis of presence/absence of (new) defects and pass/fail (of integrated circuits) is obtained. Next, in the step (S12) set is a situation where chips are randomly extracted out of all the chips with the number of chips with defect used as random extraction number on the basis of the chip classification data obtained in the step (S11). After that, in the step (S13) obtained is the random probability of failure (P(N4)) which is a probability that the number of faulty chips included in the randomly-extracted chips should be not less than the equivalent of the number (N4) of faulty chips with defect. Thus obtained is a defect analysis method and a method of verifying chip classification data, by which the analysis result on the basis of the chip classification data can be enhanced.
摘要翻译：在步骤（S11）中，获得其中多个芯片基于（新的）缺陷的存在/不存在（集成电路的通过/失败）被分类为四种的芯片分类数据。接下来，在步骤（S12）中，基于在步骤（S11）中获得的芯片分类数据，设置以具有缺陷的芯片数目的所有芯片随机提取芯片作为随机提取数的情况。之后，得到的步骤（S13）是随机提取的码片中包含的有缺陷的码片的数量不应小于等于数字的概率（P（N4））） N4）故障芯片缺陷。这样获得的是一种验证芯片分类数据的缺陷分析方法和方法，通过该方法可以提高基于芯片分类数据的分析结果。

10. 发明授权

US06646306B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06646306B2
公开(公告)日：2003-11-11
申请号：US09985020
申请日：2001-11-01
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
IPC分类号： H01L2701
CPC分类号： H01L21/76286 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/458
摘要： A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.
摘要翻译：一种防止金属污染的半导体器件以及半导体器件的制造方法。区域（NR）和区域（PR）由沟槽隔离氧化膜，选择性地设置在沟槽隔离氧化膜上的多晶硅膜，设置在多晶硅膜上的硅层和设置在侧面上的侧壁隔离物多晶硅膜的表面。多晶硅膜设置在对应于跨越两个阱区域的SOI层中的P型阱区域和N型阱区域的PN结部分JP的顶部的位置。

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