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1. 发明授权

US6016562A Inspection data analyzing apparatus for in-line inspection with enhanced display of inspection results 失效
标题翻译：检查数据分析仪器，用于在线检测，增强了检测结果的显示
公开(公告)号：US6016562A
公开(公告)日：2000-01-18
申请号：US919166
申请日：1997-08-28
申请人： Yoko Miyazaki , Nobuyoshi Hattori , Junko Izumitani , Masahiko Ikeno
发明人： Yoko Miyazaki , Nobuyoshi Hattori , Junko Izumitani , Masahiko Ikeno
IPC分类号： H01L21/66 , G01R31/01 , G01R31/28 , G06F11/10
CPC分类号： G01R31/01 , G01R31/2831 , H01L22/12
摘要： An ordinary user can easily learn a step at which a problem occurs during semiconductor manufacturing processes and improve the yield of manufacturing products and the quality of the products. At a certain in-line inspection step, a CPU (3) stores data signals (V1) taken by an inspection apparatus (1) into a memory (2), and reads a result (V6) obtained at a precedent step and stores the same in the memory (2). The CPU (3) reads stored data signals (V2) from the memory (2), performs comparison or referral on data about defects which are detected at a current step and the result (V6) regarding the precedent step, and generates a defect data analysis processing result signal (V5) regarding the current step. The result (V5) consists of disappeared defect data, common defect data, new defect data to which a label of a current step number is assigned, and reappeared defect data. The CPU (3) performs the processing above for each in-line inspection step, edits resultant data, and generates histogram data which provide the number of detected defects and the number of disappeared defects for each step.
摘要翻译：普通用户可以轻松地学习在半导体制造过程中发生问题的步骤，并提高制造产品的产量和产品的质量。在某个在线检查步骤中，CPU（3）将由检查装置（1）取得的数据信号（V1）存储到存储器（2）中，并读取在先前步骤获得的结果（V6）在内存中相同（2）。 CPU（3）从存储器（2）读取存储的数据信号（V2），对与当前步骤检测到的缺陷有关的数据和关于先前步骤的结果（V6）进行比较或推荐，生成缺陷数据关于当前步骤的分析处理结果信号（V5）。结果（V5）由消失的缺陷数据，公共缺陷数据，分配了当前步骤编号的标签的新缺陷数据和重新出现的缺陷数据组成。 CPU（3）对于每个在线检查步骤执行上述处理，编辑结果数据，并且生成提供检测到的缺陷数量和每个步骤的消失缺陷数量的直方图数据。

2. 发明授权

US07423301B2 Semiconductor device including fuse elements and bonding pad 有权
标题翻译：半导体器件包括熔丝元件和焊盘
公开(公告)号：US07423301B2
公开(公告)日：2008-09-09
申请号：US11697760
申请日：2007-04-09
申请人： Noriaki Fujiki , Takashi Yamashita , Junko Izumitani
发明人： Noriaki Fujiki , Takashi Yamashita , Junko Izumitani
IPC分类号： H01L27/10
CPC分类号： H01L24/03 , H01L23/5258 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05082 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48724 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.
摘要翻译：半导体器件包括下层衬底，在下层衬底上方的熔丝并用光照射，熔丝上的氧化硅膜和下层衬底的表面的暴露部分上的硅氧化硅膜上的氮化物膜。下层基板的表面上的氧化硅膜的部分比熔丝厚，氧化硅膜具有与保险丝相对的开口。

3. 发明授权

US06645863B2 Method of manufacturing semiconductor device and semiconductor device 失效
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US06645863B2
公开(公告)日：2003-11-11
申请号：US09986001
申请日：2001-11-07
申请人： Hiroki Takewaka , Takao Kamoshima , Junko Izumitani
发明人： Hiroki Takewaka , Takao Kamoshima , Junko Izumitani
IPC分类号： H01L2100
CPC分类号： H01L21/7684 , H01L21/28556 , H01L21/3212 , H01L21/76877 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a method of manufacturing a semiconductor device which can reduce or prevent abrasive material from remaining in an indentation in a surface after a CMP process. After forming a titanium nitride film (5), a tungsten film (6) is formed on an entire surface. The temperature is set at approximately 430° C. for the reaction and, first, 50 sccm of WF6, 10 sccm of SiH4 and 1000 sccm of H2 are used in the atmosphere of 30 Torr of Ar, N2 so as to form a seed layer with a film thickness of approximately 100 nm. After that, in the atmosphere of 80 Torr of Ar, N2, 75 sccm of WF6 and 500 sccm of H2 are used as a reactive gas so as to layer a film with a thickness of approximately 300 nm. The tungsten film (6) has grains (6a) in a pillar form of which the grain diameter is small to the degree that the abrasive material (50) used in the CMP process does not easily become caught in the gaps between the grains. Concretely, the tungsten film (6) has grains (6a) of which the diameter is approximately 10 nm to 20 nm.
摘要翻译：本发明提供一种半导体器件的制造方法，其可以在CMP工艺之后减少或防止研磨材料残留在表面的压痕中。在形成氮化钛膜（5）之后，形成钨膜（6）整个表面。对于反应，温度设定在约430℃，首先在30托的Ar，N2的气氛中使用50sccm的WF6，10sccm的SiH4和1000sccm的H 2，以形成种子层膜厚度约为100nm。之后，在80Torr的Ar，N2的气氛中，使用75sccm的WF6和500sccm的H 2作为反应气体，以便层厚约300nm的膜。钨膜（6）具有柱状晶粒（6a），其晶粒直径小到在CMP工艺中使用的研磨材料（50）不容易被捕获在晶粒之间的间隙中的程度。具体地说，钨膜（6）具有直径约为10nm〜20nm的晶粒（6a）。

4. 发明授权

US06333259B1 Semiconductor device and apparatus and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06333259B1
公开(公告)日：2001-12-25
申请号：US09263771
申请日：1999-03-05
申请人： Junko Izumitani , Kazuyoshi Maekawa
发明人： Junko Izumitani , Kazuyoshi Maekawa
IPC分类号： H01L214763
CPC分类号： C23C14/541 , C23C14/022 , H01L21/67155 , H01L21/76877 , Y10S438/908 , Y10S438/952
摘要： Disclosed is an apparatus for manufacturing a semiconductor device including a metal film which is formed on a semiconductor substrate in a film formation region containing the interior of a hole formed in the semiconductor substrate. The apparatus includes a degassing chamber, a film forming chamber, and a cooing chamber. The degassing chamber 34 is provided for carrying out a degassing process by heating the semiconductor substrate to a degassing temperature. The film forming chamber 40 is provided for forming a metal film on the film formation region in a state in which the semiconductor substrate is heated to a film formation temperature. The cooling chamber 38 is provided for cooling, after completion of the degassing process and before beginning of the formation of the metal film, the semiconductor substrate to a cold temperature being lower than the film formation temperature and in a range of −50° C. to 150° C.
摘要翻译：公开了一种半导体器件的制造方法，该半导体器件包括金属膜，该金属膜形成在半导体衬底上的成膜区域中，所述成膜区域包含形成在半导体衬底中的孔的内部。该装置包括脱气室，成膜室和冷却室。脱气室34设置用于通过将半导体衬底加热至脱气温度来进行脱气过程。膜形成室40被设置用于在将半导体衬底加热到成膜温度的状态下在成膜区域上形成金属膜。冷却室38被设置用于冷却，在完成脱气处理之后并且在开始形成金属膜之前，将半导体衬底冷却到低于成膜温度并在-50℃的范围内。至150℃

5. 发明申请

US20100052062A1 SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100052062A1
公开(公告)日：2010-03-04
申请号：US12502008
申请日：2009-07-13
申请人： Shoichi Fukui , Noboru Morimoto , Yasutaka Nishioka , Junko Izumitani , Atsushi Ishii
发明人： Shoichi Fukui , Noboru Morimoto , Yasutaka Nishioka , Junko Izumitani , Atsushi Ishii
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76819 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/76849 , H01L21/76867 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.
摘要翻译：提供能提高半导体器件的可靠性的半导体器件的制造方法。用于覆盖形成在半导体衬底中的半导体元件的第一绝缘膜通过具有良好嵌入特性的热CVD法等形成。通过等离子体CVD法形成第二绝缘膜以覆盖第一绝缘膜，其具有优异的耐湿性。形成插塞以穿透第一绝缘膜和第二绝缘膜。在第二绝缘膜上形成由具有较低介电常数的低k膜构成的第三绝缘膜。通过镶嵌技术在第三绝缘膜中形成布线以与插头电耦合。

6. 发明授权

US06727590B2 Semiconductor device with internal bonding pad 失效
标题翻译：具有内部接合垫的半导体器件
公开(公告)号：US06727590B2
公开(公告)日：2004-04-27
申请号：US10136533
申请日：2002-05-02
申请人： Junko Izumitani , Hiroki Takewaka
发明人： Junko Izumitani , Hiroki Takewaka
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L23/5226 , H01L23/53214 , H01L23/53228 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05006 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05644 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/48744 , H01L2224/48799 , H01L2224/48824 , H01L2224/48844 , H01L2224/85201 , H01L2224/85205 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01039 , H01L2924/0105 , H01L2924/01068 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/13091 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2924/00015 , H01L2924/01004
摘要： A semiconductor device has a multilayer interconnection structure in which a plurality of interconnection layers is formed in an insulating film. The multilayer interconnection structure has a first metal film made of a first material and functioning as a first interconnection belonging to an interconnection layer other than an uppermost interconnection layer, a second metal film made of a second material and functioning as a second interconnection belonging to the uppermost interconnection layer, a third metal film made of the first material and belonging to an interconnection layer other than the uppermost interconnection layer and functioning as a bonding pad, an opening formed in the insulating film and having its bottom defined by the third metal film, and a bonding wire connected to the third metal film through the opening. The second material has a lower resistance and is more susceptible to oxidation than the first material.
摘要翻译：半导体器件具有多层互连结构，其中在绝缘膜中形成多个互连层。所述多层互连结构具有由第一材料制成的第一金属膜，并且用作属于第一互连的第一互连，所述第一互连属于除最上层互连层之外的互连层，第二金属膜由第二材料制成并用作第二互连属于最上面的互连层，由第一材料制成并且属于最上层互连层以外的互连层并用作接合焊盘的第三金属膜，形成在绝缘膜中并具有由第三金属膜限定的底部的开口，以及通过开口连接到第三金属膜的接合线。第二种材料具有较低的电阻，比第一种材料更易于氧化。

7. 发明授权

US06890857B2 Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion, and method for fabricating the same 失效
标题翻译：具有多层布线结构的半导体器件和防腐蚀的焊盘电极及其制造方法
公开(公告)号：US06890857B2
公开(公告)日：2005-05-10
申请号：US10281162
申请日：2002-10-28
申请人： Shigeru Harada , Yoshifumi Takata , Junko Izumitani
发明人： Shigeru Harada , Yoshifumi Takata , Junko Izumitani
IPC分类号： H01L23/52 , H01L21/304 , H01L21/3205 , H01L21/60 , H01L23/485 , H01L21/302 , H01L21/461
CPC分类号： H01L24/48 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05073 , H01L2224/05093 , H01L2224/05124 , H01L2224/05647 , H01L2224/05669 , H01L2224/16 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48647 , H01L2224/48669 , H01L2224/48747 , H01L2224/48769 , H01L2224/48799 , H01L2224/48847 , H01L2224/48869 , H01L2224/7865 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85375 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2224/78 , H01L2924/00 , H01L2924/00015
摘要： The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.
摘要翻译：本发明提供一种能够防止焊盘电极的表面氧化，提高焊盘电极与外部端子之间的连接强度的半导体装置。根据本发明的半导体器件包括用于连接外部电极的焊盘电极和连接到焊盘电极的多层布线结构，其中绝缘层的一个表面覆盖焊盘电极并且在焊盘电极上方具有用于暴露表面的开口的焊盘电极与从贵金属和贵金属的合金中选择的一种金属层作为主要成分接触。

8. 发明授权

US06500675B2 Manufacturing method of semiconductor device having capacitive element 失效
标题翻译：具有电容元件的半导体器件的制造方法
公开(公告)号：US06500675B2
公开(公告)日：2002-12-31
申请号：US09837461
申请日：2001-04-19
申请人： Yoshifumi Takata , Junko Izumitani , Shigeki Sunada
发明人： Yoshifumi Takata , Junko Izumitani , Shigeki Sunada
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/76838 , H01L28/75
摘要： A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.
摘要翻译：用于电容元件的电介质层形成在下电极上。在下电极和电容元件的电介质层上形成层间绝缘层。在层间绝缘层中形成到达用于电容元件的电介质层的插塞孔。上电极形成为填充插塞孔并与下电极相对定位，其中插入用于电容元件的电介质层。用于电容元件的电介质层在插塞孔正下方的区域和插塞孔的侧壁外侧的区域与下电极的上表面接触。因此，提供了具有防止金属原子从下部电极扩散的具有较大电容的电容元件的半导体器件及其制造方法。

9. 发明授权

US07335537B2 Method of manufacturing semiconductor device including bonding pad and fuse elements 有权
标题翻译：制造包括接合焊盘和熔丝元件的半导体器件的方法
公开(公告)号：US07335537B2
公开(公告)日：2008-02-26
申请号：US11697765
申请日：2007-04-09
申请人： Noriaki Fujiki , Takashi Yamashita , Junko Izumitani
发明人： Noriaki Fujiki , Takashi Yamashita , Junko Izumitani
IPC分类号： H01L21/82
CPC分类号： H01L24/03 , H01L23/5258 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05082 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48724 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.
摘要翻译：一种制造半导体器件的方法包括：形成由半导体衬底支撑的第一绝缘膜，形成由第一绝缘膜支撑的铝层，蚀刻铝层以形成接合焊盘和熔丝元件，通过等离子体化学气相沉积法沉积覆盖接合焊盘和熔丝元件的第二绝缘膜，第二绝缘膜在熔丝元件和与熔丝元件相对的脊部之间具有平面部分，通过等离子体化学气相沉积沉积覆盖第二绝缘膜的第三绝缘膜，蚀刻第三绝缘膜绝缘膜以形成暴露第二绝缘膜的与熔丝元件相对的第一区域的第一孔和暴露第二绝缘膜的与至少部分所述焊盘相对的第二区域的第二孔，并蚀刻第二绝缘层膜以形成暴露至少部分焊盘的第三孔。

10. 发明授权

US06476491B2 Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion and method for fabricating the same 失效
标题翻译：具有多层布线结构的半导体器件和防腐蚀的焊盘电极及其制造方法
公开(公告)号：US06476491B2
公开(公告)日：2002-11-05
申请号：US09756908
申请日：2001-01-10
申请人： Shigeru Harada , Yoshifumi Takata , Junko Izumitani
发明人： Shigeru Harada , Yoshifumi Takata , Junko Izumitani
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05073 , H01L2224/05093 , H01L2224/05124 , H01L2224/05647 , H01L2224/05669 , H01L2224/16 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48647 , H01L2224/48669 , H01L2224/48747 , H01L2224/48769 , H01L2224/48799 , H01L2224/48847 , H01L2224/48869 , H01L2224/7865 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85375 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2224/78 , H01L2924/00 , H01L2924/00015
摘要： The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer. formed from one selected from precious metals and alloys containing the precious metals as main components.
摘要翻译：本发明提供一种能够防止焊盘电极的表面的氧化以提高焊盘电极与外部端子之间的连接强度的半导体装置。根据本发明的半导体器件包括用于连接外部电极的焊盘电极和连接到焊盘电极的多层布线结构，其中绝缘层的一个表面覆盖焊盘电极并且在焊盘电极上方具有用于暴露表面的开口的焊盘电极与金属层接触。由选自贵金属和贵金属的合金作为主要成分的一种形成。

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