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1. 发明授权

US06054872A Semiconductor integrated circuit with mixed gate array and standard cell 失效
标题翻译：具有混合门阵列和标准单元的半导体集成电路
公开(公告)号：US06054872A
公开(公告)日：2000-04-25
申请号：US997035
申请日：1997-12-23
申请人： Nobuo Fudanuki , Toshikazu Sei
发明人： Nobuo Fudanuki , Toshikazu Sei
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1735
摘要： The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.
摘要翻译：本发明涉及一种半定制ASIC，其中布置有多个标准单元行。门阵列中使用的标准单元和基本单元混合安装在同一芯片上。各个单元行由具有空白空间的多个标准单元组成。门阵列中使用的基本单元被布置为虚拟单元。它们被布置在同一标准单元行中的标准单元之间的多个标准单元之间的布线沟道区域或空白空间中。如果采用无通道型标准电池，则只能使用后者。当需要改变电路设计或图案时，可以通过在栅极阵列基本单元上形成金属布线层来满足变化的要求。由于可以在不改变栅极多晶硅区域和金属布线层下面的源极/漏极区域的情况下修改电路，因此可以在短时间内实现设计和制造。

2. 再颁专利

USRE39469E1 Semiconductor integrated circuit with mixed gate array and standard cell 失效
标题翻译：具有混合门阵列和标准单元的半导体集成电路
公开(公告)号：USRE39469E1
公开(公告)日：2007-01-16
申请号：US09963735
申请日：2001-09-27
申请人： Nobuo Fudanuki , Toshikazu Sei
发明人： Nobuo Fudanuki , Toshikazu Sei
IPC分类号： H03K19/177
CPC分类号： H03K19/1735
摘要： The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.
摘要翻译：本发明涉及一种半定制ASIC，其中布置有多个标准单元行。门阵列中使用的标准单元和基本单元混合安装在同一芯片上。各个单元行由具有空白空间的多个标准单元组成。门阵列中使用的基本单元被布置为虚拟单元。它们被布置在同一标准单元行中的标准单元之间的多个标准单元之间的布线沟道区域或空白空间中。如果采用无通道型标准电池，则只能使用后者。当需要改变电路设计或图案时，可以通过在栅极阵列基本单元上形成金属布线层来满足变化的要求。由于可以在不改变栅极多晶硅区域和金属布线层下面的源极/漏极区域的情况下修改电路，因此可以在短时间内实现设计和制造。

3. 发明授权

US4584642A Logic simulation apparatus 失效
标题翻译：逻辑仿真装置
公开(公告)号：US4584642A
公开(公告)日：1986-04-22
申请号：US543300
申请日：1983-10-19
申请人： Nobuo Fudanuki
发明人： Nobuo Fudanuki
IPC分类号： G01R31/28 , G06F11/25 , G06F17/50 , G06F19/00 , H03K19/00 , G06F15/20
CPC分类号： G06F17/5022
摘要： A logic simulation apparatus has a data memory for storing node level data of a logic circuit, a command memory for storing interconnection data which comprises an input data address, an output data address, a fan-out address and a function of module, and a data processing circuit for simulating the operation for each module in accordance with the commands read out from the command memory. The read address of the command memory is accessed by an address counter which is incremented by one for every read operation. The fan-out address read out from the command memory is written in an address queue, and when a simulation of one module is completed, the fan-out address is read out from the address queue and set in the address counter in order to start a simulation of a next module.
摘要翻译：逻辑模拟装置具有用于存储逻辑电路的节点电平数据的数据存储器，用于存储互连数据的命令存储器，其包括输入数据地址，输出数据地址，扇出地址和模块的功能，以及数据处理电路，用于根据从命令存储器读出的命令模拟每个模块的操作。命令存储器的读地址由地址计数器访问，每个读操作都增加一个地址计数器。从命令存储器读出的扇出地址写入地址队列，当一个模块的模拟完成时，扇出地址从地址队列中读出并设置在地址计数器中，以便启动模拟下一个模块。

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