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1. 发明授权

US06323510B1 Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45° angles 失效
标题翻译：具有包括45°角的选择晶体管和辅助电容布线的存储单元阵列的半导体存储器件
公开(公告)号：US06323510B1
公开(公告)日：2001-11-27
申请号：US09023819
申请日：1998-02-13
申请人： Nobuhiro Tanabe , Kazushi Amanuma
发明人： Nobuhiro Tanabe , Kazushi Amanuma
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A semiconductor memory device is provided, which prevents the characteristic of storage capacitors from degrading without chip-area increase of memory cells. Each of storage capacitors has a dielectric sandwiched by lower and upper electrodes. The lower electrodes are formed by a patterned, common electrically-conductive layer. The dielectrics are formed by a patterned, common ferroelectric layer formed on the common electrically-conductive layer which is entirely overlapped with the common electrically-conductive layer. The upper electrodes are regularly arranged on the common ferroelectric layer and are located outside the rows and columns of a matrix array where the windows of the common electrically-conductive layer and common ferroelectric layer are aligned. Wiring lines are formed over the upper electrodes through an interlayer insulating layer covering the storage capacitors, thereby electrically connecting the upper electrodes and select transistors.
摘要翻译：提供一种半导体存储器件，其防止存储电容器的特性降低，而不会存储单元的芯片面积增加。每个存储电容器具有由下电极和上电极夹持的电介质。下电极由图案化的公共导电层形成。电介质由形成在公共导电层上的图案化的公共铁电层形成，该公共导电层与公共导电层完全重叠。上电极规则地布置在公共铁电层上，并且位于公共导电层和公共铁电层的窗口对齐的矩阵阵列的行和列的外侧。通过覆盖存储电容器的层间绝缘层在上电极上形成配线，从而电连接上电极和选择晶体管。

2. 发明授权

US06603203B2 Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same 有权
标题翻译：具有电容元件结构和多层互连结构的半导体器件及其制造方法
公开(公告)号：US06603203B2
公开(公告)日：2003-08-05
申请号：US09902608
申请日：2001-07-12
申请人： Kazushi Amanuma
发明人： Kazushi Amanuma
IPC分类号： H01L2348
CPC分类号： H01L28/40 , H01L21/76838 , H01L27/10855
摘要： A capacitive element structure in a semiconductor device having an interconnection structure. The capacitive element structure includes a capacitive element having a capacitive dielectric film made of an oxide compound. The capacitive element structure is above at least a bottom level interconnection of the interconnection structure.
摘要翻译：具有互连结构的半导体器件中的电容元件结构。电容元件结构包括具有由氧化物化合物制成的电容性电介质膜的电容元件。电容元件结构在互连结构的至少底层互连之上。

3. 发明授权

US06395612B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06395612B1
公开(公告)日：2002-05-28
申请号：US09718832
申请日：2000-11-22
申请人： Kazushi Amanuma
发明人： Kazushi Amanuma
IPC分类号： H01L2120
CPC分类号： H01L28/55
摘要： A semiconductor device has a device isolation oxide film, an interlayer insulating film, hydrogen barrier films, a lower electrode, a capacitor insulating film, an upper electrode, an interlayer insulating film and a wiring layer, formed on a silicon substrate. A gate electrode is formed on a gate oxide film between impurity diffusion regions in the silicon substrate. Further, a capacitor portion, comprising the lower electrode, the capacitor insulating film (ferroelectric or high dielectric substance) and the upper electrode, is completely covered with the hydrogen barrier films. The hydrogen barrier films prevent deterioration of the ferroelectric substance and the high dielectric constant material due to reducing conditions in a hydrogen atmosphere. Other device characteristics, however, are not adversely affected because only the capacitor portion is completely covered with the hydrogen barrier films.
摘要翻译：半导体器件具有在硅衬底上形成的器件隔离氧化膜，层间绝缘膜，氢阻挡膜，下电极，电容器绝缘膜，上电极，层间绝缘膜和布线层。在硅衬底中的杂质扩散区之间的栅极氧化膜上形成栅电极。此外，包括下电极，电容器绝缘膜（铁电体或高介电体）和上电极的电容器部分被氢阻挡膜完全覆盖。氢阻挡膜由于氢气氛中的还原条件而防止铁电体和高介电常数材料的劣化。然而，其他器件特性不会受到不利影响，因为只有电容器部分被氢阻挡膜完全覆盖。

4. 发明授权

US06316801B1 Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same 有权
标题翻译：具有电容元件结构和多层互连结构的半导体器件及其制造方法
公开(公告)号：US06316801B1
公开(公告)日：2001-11-13
申请号：US09262070
申请日：1999-03-04
申请人： Kazushi Amanuma
发明人： Kazushi Amanuma
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L21/76838 , H01L27/10855
摘要： A capacitive element structure in a semiconductor device having an interconnection structure. The capacitive element structure includes a capacitive element having a capacitive dielectric film made of an oxide compound. The capacitive element structure is above at least a first level interconnection of the interconnection structure.
摘要翻译：具有互连结构的半导体器件中的电容元件结构。电容元件结构包括具有由氧化物化合物制成的电容电介质膜的电容元件。电容元件结构在互连结构的至少第一级互连之上。

5. 发明授权

US06281536B1 Ferroelectric memory device with improved ferroelectric capacity characteristic 有权
标题翻译：具有改进的铁电容量特性的铁电存储器件
公开(公告)号：US06281536B1
公开(公告)日：2001-08-28
申请号：US09287413
申请日：1999-04-07
申请人： Sota Shinohara , Kazushi Amanuma , Yukinobu Murao , Yuukoh Katoh , Tsuneo Takeuchi , Yoshihiro Hayashi
发明人： Sota Shinohara , Kazushi Amanuma , Yukinobu Murao , Yuukoh Katoh , Tsuneo Takeuchi , Yoshihiro Hayashi
IPC分类号： H01L2972
CPC分类号： H01L27/11502 , H01L28/55
摘要： A ferroelectric memory device includes a ferroelectric capacitance element formed through an insulating film on a semiconductor substrate. The ferroelectric capacitance element includes a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. The upper electrode has a laminate structure which contains a conductive oxide layer of first metal which is connected with the ferroelectric film.
摘要翻译：铁电存储器件包括通过半导体衬底上的绝缘膜形成的铁电电容元件。铁电电容元件包括下电极，形成在下电极上的铁电膜和形成在铁电体膜上的上电极。上部电极具有包含与铁电体膜连接的第一金属的导电性氧化物层的层叠结构。

6. 发明授权

US06188098B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06188098B1
公开(公告)日：2001-02-13
申请号：US09178620
申请日：1998-10-26
申请人： Kazushi Amanuma
发明人： Kazushi Amanuma
IPC分类号： H01L27108
CPC分类号： H01L28/55
摘要： A semiconductor device has a device isolation oxide film, an interlayer insulating film, hydrogen barrier films, a lower electrode, a capacitor insulating film, an upper electrode, an interlayer insulating film and a wiring layer, formed on a silicon substrate. A gate electrode is formed on a gate oxide film between impurity diffusion regions in the silicon substrate. Further, a capacitor portion, comprising the lower electrode, the capacitor insulating film (ferroelectric or high dielectric substance) and the upper electrode, is completely covered with the hydrogen barrier films. The hydrogen barrier films prevent deterioration of the ferroelectric substance and the high dielectric constant material due to reducing conditions in a hydrogen atmosphere. Other device characteristics, however, are not adversely affected because only the capacitor portion is completely covered with the hydrogen barrier films.
摘要翻译：半导体器件具有在硅衬底上形成的器件隔离氧化膜，层间绝缘膜，氢阻挡膜，下电极，电容器绝缘膜，上电极，层间绝缘膜和布线层。在硅衬底中的杂质扩散区之间的栅极氧化膜上形成栅电极。此外，包括下电极，电容器绝缘膜（铁电体或高介电体）和上电极的电容器部分被氢阻挡膜完全覆盖。氢阻挡膜由于氢气氛中的还原条件而防止铁电体和高介电常数材料的劣化。然而，其他器件特性不会受到不利影响，因为只有电容器部分被氢阻挡膜完全覆盖。

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