会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 3. 发明授权
      US6004839A Semiconductor device with conductive plugs 失效
    • Semiconductor device with conductive plugs
    • 带导电插头的半导体器件
    • US6004839A
    • 1999-12-21
    • US804112
    • 1997-02-20
    • Yoshihiro Hayashi , Nobuhiro Tanabe , Tsuneo Takeuchi , Shinobu Saito
    • Yoshihiro Hayashi , Nobuhiro Tanabe , Tsuneo Takeuchi , Shinobu Saito
    • H01L21/768 , H01L21/8242 , H01L21/8246 , H01L21/8238
    • H01L27/11502 , H01L21/768 , H01L27/10844 , H01L27/10852 , H01L27/11507
    • In a method of manufacturing a semiconductor device, a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor is formed on a substrate. A plurality of conductive plugs is formed to penetrate a laminate insulating film to the MOS transistors. The laminate insulating film is composed of a first insulating film and a second insulating film. A capacitor section is formed on the laminate insulating film and the capacitor section is composed of an upper electrode, a dielectric film and a lower electrode. A third insulating film is formed on the laminate insulating film and the capacitor section. A wiring pattern is formed on the third insulating film to partially penetrate the second insulating film connect to the plurality of conductive plugs. A wiring pattern may be disposed in the laminate insulating film to connect at least two of the plurality of conductive plugs.
    • 在制造半导体器件的方法中，在衬底上形成由N沟道MOS晶体管和P沟道MOS晶体管组成的CMOS部分和至少由传输门MOS晶体管组成的存储部分。 形成多个导电插塞以穿透层压绝缘膜到MOS晶体管。 层叠绝缘膜由第一绝缘膜和第二绝缘膜构成。 在层叠绝缘膜上形成电容器部，电容部由上部电极，电介质膜和下部电极构成。 在层压绝缘膜和电容器部分上形成第三绝缘膜。 在第三绝缘膜上形成布线图案，以部分地穿透连接到多个导电插塞的第二绝缘膜。 布线图案可以布置在层压绝缘膜中以连接多个导电插塞中的至少两个。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US06323510B1 Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45° angles 失效
    • Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45° angles
    • 具有包括45°角的选择晶体管和辅助电容布线的存储单元阵列的半导体存储器件
    • US06323510B1
    • 2001-11-27
    • US09023819
    • 1998-02-13
    • Nobuhiro Tanabe , Kazushi Amanuma
    • Nobuhiro Tanabe , Kazushi Amanuma
    • H01L2976
    • H01L27/11502 , H01L27/11507
    • A semiconductor memory device is provided, which prevents the characteristic of storage capacitors from degrading without chip-area increase of memory cells. Each of storage capacitors has a dielectric sandwiched by lower and upper electrodes. The lower electrodes are formed by a patterned, common electrically-conductive layer. The dielectrics are formed by a patterned, common ferroelectric layer formed on the common electrically-conductive layer which is entirely overlapped with the common electrically-conductive layer. The upper electrodes are regularly arranged on the common ferroelectric layer and are located outside the rows and columns of a matrix array where the windows of the common electrically-conductive layer and common ferroelectric layer are aligned. Wiring lines are formed over the upper electrodes through an interlayer insulating layer covering the storage capacitors, thereby electrically connecting the upper electrodes and select transistors.
    • 提供一种半导体存储器件，其防止存储电容器的特性降低，而不会存储单元的芯片面积增加。 每个存储电容器具有由下电极和上电极夹持的电介质。 下电极由图案化的公共导电层形成。 电介质由形成在公共导电层上的图案化的公共铁电层形成，该公共导电层与公共导电层完全重叠。 上电极规则地布置在公共铁电层上，并且位于公共导电层和公共铁电层的窗口对齐的矩阵阵列的行和列的外侧。 通过覆盖存储电容器的层间绝缘层在上电极上形成配线，从而电连接上电极和选择晶体管。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5391901A Semiconductor memory with oblique folded bit-line arrangement 失效
    • Semiconductor memory with oblique folded bit-line arrangement
    • 具有倾斜折叠位线布置的半导体存储器
    • US5391901A
    • 1995-02-21
    • US139718
    • 1993-10-22
    • Nobuhiro Tanabe
    • Nobuhiro Tanabe
    • H01L27/10 , H01L21/8242 , H01L27/108 , H01L23/48
    • H01L27/10805
    • A plurality of word lines extend linearly and parallel to each other. A reference word line is positioned to divide the word lines into two groups of word lines. A plurality of bit lines are folded on the reference word line symmetrically with respect to the reference word line and spaced at intervals from each other. Each of memory elements comprises a capacitive element and a switching transistor having a source connected to the capacitive element, a drain connected to one of the bit lines, and a gate connected to one of the word lines. The memory elements are disposed in a matrix such that they are spaced across and along the word lines and paired memory elements whose switching transistors have drains connected to the same bit line are positioned symmetrically with respect to the reference word line.
    • 多个字线线性地并且彼此平行地延伸。 一个参考字线被定位成将字线分成两组字线。 多个位线在参考字线上相对于参考字线对称地折叠并且彼此间隔开。 每个存储元件包括电容元件和具有连接到电容元件的源极的开关晶体管，连接到位线之一的漏极和连接到字线之一的栅极。 存储器元件以矩阵的形式设置，使得它们沿着字线间隔开并且沿着字线间隔开并且成对的存储器元件，其开关晶体管具有连接到相同位线的漏极相对于参考字线对称地定位。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号