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1. 发明授权

US4892613A Process for etching light-shielding thin film 失效
标题翻译：蚀刻光屏蔽薄膜的工艺
公开(公告)号：US4892613A
公开(公告)日：1990-01-09
申请号：US290076
申请日：1988-12-27
申请人： Noboru Motai , Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yaeko Suzuki , Yoshihisa Ogiwara , Kazunori Saito , Keiko Shibuki
发明人： Noboru Motai , Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yaeko Suzuki , Yoshihisa Ogiwara , Kazunori Saito , Keiko Shibuki
IPC分类号： H01L21/302 , H01L21/027 , H01L21/28 , H01L21/3065 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66765 , H01L21/0274 , H01L21/28008 , H01L29/78633
摘要： A light shielding thin film is provided on a light transmitting substrate, and the film is covered by a photoresist. The photoresist is exposed and developed to form a pattern, and the film is etched using the pattern as a mask. The pattern is then exposed through the substrate, using the film as a mask, the pattern then being developed to form a pattern of reduced size. The film is then etched using the reduced size pattern as a mask.
摘要翻译：在透光性基板上设置遮光薄膜，由光致抗蚀剂覆盖薄膜。光致抗蚀剂被曝光和显影以形成图案，并且使用该图案作为掩模蚀刻该膜。然后将该图案通过基底曝光，使用该膜作为掩模，然后将该图案显影以形成尺寸减小的图案。然后使用减小尺寸的图案作为掩模蚀刻该膜。

2. 发明授权

US5005056A Amorphous-silicon thin film transistor array substrate 失效
标题翻译：非晶硅薄膜晶体管阵列基板
公开(公告)号：US5005056A
公开(公告)日：1991-04-02
申请号：US306373
申请日：1989-02-03
申请人： Noboru Motai , Sakae Tanaka , Yoshiaki Watanabe
发明人： Noboru Motai , Sakae Tanaka , Yoshiaki Watanabe
IPC分类号： H01L23/52 , G02F1/136 , G02F1/1362 , G02F1/1368 , H01L21/3205 , H01L27/12 , H01L29/45 , H01L29/78 , H01L29/786
CPC分类号： H01L29/458 , G02F1/1368 , G02F2001/136263 , G02F2202/103
摘要： A reverse staggered amorphous-silicon thin film transistor array substrate includes amorphous silicon thin film transistors in an array, gate wirings interconnecting the gate electrodes of the transistors, and source wirings of a transparent conductive layer connecting the source electrodes. An auxiliary source wiring of the material of the source electrodes of said transistors is provided under the source wiring.
摘要翻译：反向交错的非晶硅薄膜晶体管阵列基板包括阵列中的非晶硅薄膜晶体管，互连晶体管的栅极的栅极布线和连接源电极的透明导电层的源极布线。所述晶体管的源电极的材料的辅助源极布线设置在源极布线的下方。

3. 发明授权

US5109260A Silicon thin film transistor and method for producing the same 失效
标题翻译：硅薄膜晶体管及其制造方法
公开(公告)号：US5109260A
公开(公告)日：1992-04-28
申请号：US564815
申请日：1990-08-08
申请人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
发明人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
IPC分类号： H01L21/336 , H01L29/417 , H01L29/786
CPC分类号： H01L29/66765 , H01L29/41733 , H01L29/78618 , H01L29/78621 , H01L29/78624
摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.
摘要翻译：硅薄膜晶体管阵列包括阵列状形式的多个硅薄膜晶体管，每个硅薄膜晶体管包括绝缘基板，形成在绝缘基板上的栅电极，形成在绝缘基板上的栅绝缘层，栅电极，一对第一杂质含有在栅极绝缘层上形成的跨越栅电极的端部的硅层，形成在一对第一杂质上的本征硅层含有硅层和在一对第一杂质之间的栅极绝缘层包含硅层，以便连接一对第一杂质含硅层，形成在本征硅层上的保护绝缘层，以及形成在源极电极和漏电极该对第一杂质的接触部分含有硅层; 用于将硅薄膜晶体管的栅电极彼此连接的栅极布线; 以及用于将硅薄膜晶体管的源电极彼此连接的源极布线。

4. 发明授权

US5065202A Amorphous silicon thin film transistor array substrate and method for producing the same 失效
标题翻译：非晶硅薄膜晶体管阵列基板及其制造方法
公开(公告)号：US5065202A
公开(公告)日：1991-11-12
申请号：US534003
申请日：1990-06-04
申请人： Sakae Tanaka , Yoshiaki Watanabe
发明人： Sakae Tanaka , Yoshiaki Watanabe
IPC分类号： H01L23/52 , G02F1/136 , G02F1/1368 , H01L21/31 , H01L21/3205 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78669 , H01L27/1214
摘要： An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, as gate wiring itnerconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.
摘要翻译：在具有栅极绝缘层的绝缘基板上形成非晶硅薄膜晶体管阵列基板，作为栅极布线与栅极电极和源极布线互连源极电极连接。栅极绝缘层设置在源极配线的端子部的下层。在形成阵列的工艺中，栅极绝缘层形成在除了栅极的端子部分之外的结构的一部分中，源极配线的端子部分形成在栅极绝缘层上。

5. 发明授权

US5122849A Silicon thin film transistor 失效
标题翻译：硅薄膜晶体管
公开(公告)号：US5122849A
公开(公告)日：1992-06-16
申请号：US564818
申请日：1990-08-08
申请人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
发明人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
IPC分类号： H01L29/786
CPC分类号： H01L29/78624 , H01L29/78618 , H01L29/78621
摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.
摘要翻译：硅薄膜晶体管阵列包括阵列状形式的多个硅薄膜晶体管，每个硅薄膜晶体管包括绝缘基板，形成在绝缘基板上的栅电极，形成在绝缘基板上的栅绝缘层，栅电极，一对第一杂质含有在栅极绝缘层上形成的跨越栅电极的端部的硅层，形成在一对第一杂质上的本征硅层含有硅层和在一对第一杂质之间的栅极绝缘层包含硅层，以便连接一对第一杂质含硅层，形成在本征硅层上的保护绝缘层，以及形成在源极电极和漏电极该对第一杂质的接触部分含有硅层; 用于将硅薄膜晶体管的栅电极彼此连接的栅极布线; 以及用于将硅薄膜晶体管的源电极彼此连接的源极布线。

6. 发明授权

US5121178A Silicon thin film transistor 失效
标题翻译：硅薄膜晶体管
公开(公告)号：US5121178A
公开(公告)日：1992-06-09
申请号：US564816
申请日：1990-08-08
申请人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
发明人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66765 , H01L29/78618 , H01L29/78621 , H01L29/78624 , H01L29/7866 , H01L29/78669
摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulating layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

7. 发明授权

US5121177A Silicon thin film transistor 失效
公开(公告)号：US5121177A
公开(公告)日：1992-06-09
申请号：US564806
申请日：1990-08-08
申请人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
发明人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66765 , H01L29/78618 , H01L29/78621 , H01L29/78624 , H01L29/7866 , H01L29/78669
摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source writing for connecting the source electrodes of the silicon thin film transistors to each other.

8. 发明授权

US5111261A Silicon thin film transistor with an intrinsic silicon active layer formed within the boundary defined by the edges of the gate electrode and the impurity containing silicon layer 失效
标题翻译：具有由栅极电极边界定义的边界内的内部硅活性层和含有硅层的含量的硅薄膜晶体管
公开(公告)号：US5111261A
公开(公告)日：1992-05-05
申请号：US564814
申请日：1990-08-08
申请人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
发明人： Sakae Tanaka , Yoshiaki Watanabe , Katsuo Shirai , Yoshihisa Ogiwara
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66765 , H01L29/78618 , H01L29/78621 , H01L29/78624 , H01L29/7866 , H01L29/78669
摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

9. 发明授权

US5034339A Method for producing amorphous silicon thin film transistor array substrate 失效
公开(公告)号：US5034339A
公开(公告)日：1991-07-23
申请号：US383120
申请日：1989-07-19
申请人： Sakae Tanaka , Yoshiaki Watanabe
发明人： Sakae Tanaka , Yoshiaki Watanabe
IPC分类号： H01L21/77 , H01L21/84
CPC分类号： H01L27/1214
摘要： A method for producing an amorphous silicon thin film transistor array substrate comprising successively coating a gate insulating layer, an amorphous silicon layer and a protective insulating layer on a glass substrate provided with a gate electrode and a gate wiring having a predetermined shape, in such a manner as to not cover the connecting terminal region of the gate wiring. A protective insulating layer is patterned into a predetermined shape. After passing through a predetermined production process to produce an amorphous silicon thin film transistor array, at least a gate wiring and a source wiring are provided. The step of patterning the protective insulating layer comprises covering the connecting terminals of the gate wiring and the exposed region of the glass substrate with a photoresist.

10. 发明授权

US5034340A Amorphous silicon thin film transistor array substrate and method for producing the same 失效
标题翻译：非晶硅薄膜晶体管阵列基板及其制造方法
公开(公告)号：US5034340A
公开(公告)日：1991-07-23
申请号：US371478
申请日：1989-06-26
申请人： Sakae Tanaka , Yoshiaki Watanabe
发明人： Sakae Tanaka , Yoshiaki Watanabe
IPC分类号： H01L23/52 , G02F1/136 , G02F1/1368 , H01L21/31 , H01L21/3205 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78669 , H01L27/1214
摘要： An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, a gate wiring interconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.
摘要翻译：非晶硅薄膜晶体管阵列基板形成在具有栅极绝缘层，栅极布线互连栅电极和源极布线互连源电极的绝缘基板上。栅极绝缘层设置在源极配线的端子部的下层。在形成阵列的工艺中，栅极绝缘层形成在除了栅极的端子部分之外的结构的一部分中，源极配线的端子部分形成在栅极绝缘层上。

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