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1. 发明申请

US20120084478A1 STACKED DIE WITH VERTICALLY-ALIGNED CONDUCTORS AND METHODS FOR MAKING THE SAME 有权
标题翻译：具有垂直对准导线器的堆叠式电池及其制造方法
公开(公告)号：US20120084478A1
公开(公告)日：2012-04-05
申请号：US12895098
申请日：2010-09-30
申请人： Nir J. Wakrat , Nick Seroff , Anthony Fai
发明人： Nir J. Wakrat , Nick Seroff , Anthony Fai
IPC分类号： G06F13/00
CPC分类号： G11C5/02 , G11C5/06
摘要： Stacked die having vertically-aligned conductors and methods for making the same are disclosed for providing a non-volatile memory, such as flash memory (e.g., NAND flash memory), for use in an electronic device.
摘要翻译：公开了具有垂直排列的导体的堆叠裸片及其制造方法，用于提供用于电子设备的非易失性存储器，例如闪速存储器（例如，NAND闪速存储器）。

2. 发明授权

US08319326B2 Stacked die with vertically-aligned conductors and methods for making the same 有权
标题翻译：具有垂直对准导体的堆叠裸片及其制造方法
公开(公告)号：US08319326B2
公开(公告)日：2012-11-27
申请号：US12895098
申请日：2010-09-30
申请人： Nir J. Wakrat , Nick Seroff , Anthony Fai
发明人： Nir J. Wakrat , Nick Seroff , Anthony Fai
IPC分类号： H01L23/02
CPC分类号： G11C5/02 , G11C5/06
摘要： Stacked die having vertically-aligned conductors and methods for making the same are disclosed for providing a non-volatile memory, such as flash memory (e.g., NAND flash memory), for use in an electronic device.
摘要翻译：公开了具有垂直排列的导体的堆叠裸片及其制造方法，用于提供用于电子设备的非易失性存储器，例如闪速存储器（例如，NAND闪速存储器）。

3. 发明授权

US08645770B2 Systems and methods for proactively refreshing nonvolatile memory 有权
标题翻译：用于主动刷新非易失性存储器的系统和方法
公开(公告)号：US08645770B2
公开(公告)日：2014-02-04
申请号：US13352998
申请日：2012-01-18
申请人： Anthony Fai
发明人： Anthony Fai
IPC分类号： G06F11/16 , G11C29/00
CPC分类号： G06F11/1068 , G06F11/076 , G06F11/106 , G11C11/406 , G11C11/40618 , G11C16/3418 , G11C29/08
摘要： System and methods for proactively refreshing portions of a nonvolatile memory including a memory system that proactively refreshes a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory, when meeting certain criteria determined from the data, may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed.
摘要翻译：用于主动刷新非易失性存储器的部分的系统和方法，所述非易失性存储器包括基于与所述部分相关联的数据来主动刷新非易失性存储器的一部分的存储器系统。数据可以包括自该部分最后刷新以来经过的时间，该部分已循环的次数以及该非易失性存储器的平均工作温度。当非易失性存储器未被访问时，非易失性存储器的一部分当满足从数据确定的某些标准时可以在停机期间主动刷新。

4. 发明授权

US08519737B2 Controller interface providing improved signal integrity 有权
标题翻译：控制器接口提供改善的信号完整性
公开(公告)号：US08519737B2
公开(公告)日：2013-08-27
申请号：US13175553
申请日：2011-07-01
申请人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
发明人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
IPC分类号： H03K17/16
CPC分类号： G06F13/4086
摘要： In one implementation, a memory device includes non-volatile memory and a memory controller communicatively coupled to the non-volatile memory over a first bus. The memory device can also include a host device interface through which the memory controller communicates with a host device over a second bus, wherein the host device interface includes an impedance calibration circuit that is adapted to calibrate a signal transmitted over the second bus by host device interface so that a source impedance associated with the signal matches, within a threshold value, a load impedance associated with the host device over the second bus.
摘要翻译：在一个实现中，存储器设备包括非易失性存储器和通过第一总线通信地耦合到非易失性存储器的存储器控制器。存储器设备还可以包括主机设备接口，存储器控制器通过该主机设备接口通过第二总线与主机设备进行通信，其中主机设备接口包括阻抗校准电路，该阻抗校准电路适于通过主机设备校准在第二总线上发送的信号接口，使得与该信号相关联的源阻抗在阈值内匹配通过第二总线与主机设备相关联的负载阻抗。

5. 发明授权

US08472274B2 Using temperature sensors with a memory device 有权
标题翻译：使用具有存储器件的温度传感器
公开(公告)号：US08472274B2
公开(公告)日：2013-06-25
申请号：US13038860
申请日：2011-03-02
申请人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
发明人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
IPC分类号： G11C7/04 , G11C11/56
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/26
摘要： In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells. The method can further include reading, by the memory device, the data from the non-volatile memory cells. The method can also include processing the read data based on, at least, the retrieved temperature information; and providing the processed data.
摘要翻译：在一个实现中，用于执行存储器操作的方法包括在存储器设备处接收从一个或多个非易失性存储器单元读取数据的请求; 以及检索与所述非易失性存储器单元相关联的存储的温度信息，其中所述温度信息与所述数据被写入所述非易失性存储器单元时的大致时间相关联。该方法还可以包括由存储器件读取来自非易失性存储器单元的数据。该方法还可以包括至少基于检索到的温度信息来处理读取的数据; 并提供处理的数据。

6. 发明申请

US20120215958A1 Variable Impedance Control for Memory Devices 有权
标题翻译：存储器件的可变阻抗控制
公开(公告)号：US20120215958A1
公开(公告)日：2012-08-23
申请号：US13032560
申请日：2011-02-22
申请人： Anthony Fai , Nicholas Seroff
发明人： Anthony Fai , Nicholas Seroff
IPC分类号： G06F13/00 , G06F12/02
CPC分类号： G11C7/1057 , G06F2213/0038 , G11C7/1084 , G11C8/10
摘要： This document generally describes systems, devices, methods, and techniques for variably controlling impedance for a memory device where multiple NVM units (e.g., NVM dies) are accessible over a shared bus. Impedance can be varied using switches that are configured to switch between a NVM unit and an impedance terminal. Switches can be adjusted during operation of a memory device so that a memory controller is connected over a shared bus to a selected single NVM unit and one or more impedance terminals. Impedance terminals can be configured to provide a relatively small load (a smaller load than an NVM unit) that is impedance matched (alone or in combination with other impedance terminals and/or a NVM unit) with a source impedance on a shared bus that is provided by a memory controller.
摘要翻译：本文件一般描述了用于可变地控制存储器件的阻抗的系统，设备，方法和技术，其中多个NVM单元（例如NVM管芯）可通过共享总线访问。可以使用配置为在NVM单元和阻抗端子之间切换的开关来改变阻抗。可以在存储器件的操作期间调整开关，使得存储器控制器通过共享总线连接到所选择的单个NVM单元和一个或多个阻抗端子。阻抗端子可以配置为提供与共享总线上的源阻抗阻抗匹配（单独或与其他阻抗端子和/或NVM单元组合）相对较小的负载（比NVM单元更小的负载）由存储器控制器提供。

7. 发明申请

US20130185606A1 SYSTEMS AND METHODS FOR PROACTIVELY REFRESHING NONVOLATILE MEMORY 有权
标题翻译：用于改进非易失性存储器的系统和方法
公开(公告)号：US20130185606A1
公开(公告)日：2013-07-18
申请号：US13352998
申请日：2012-01-18
申请人： Anthony Fai
发明人： Anthony Fai
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F11/1068 , G06F11/076 , G06F11/106 , G11C11/406 , G11C11/40618 , G11C16/3418 , G11C29/08
摘要： System and methods for proactively refreshing portions of a nonvolatile memory are disclosed. A memory system may proactively refresh a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory meeting certain criteria determined from that data may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed.
摘要翻译：公开了用于主动刷新非易失性存储器的部分的系统和方法。存储器系统可以基于与该部分相关联的数据主动地刷新非易失性存储器的一部分。数据可以包括自该部分最后刷新以来经过的时间，该部分已循环的次数以及该非易失性存储器的平均工作温度。满足从该数据确定的某些标准的非易失性存储器的一部分可以在非易失性存储器未被访问的停机期间被主动刷新。

8. 发明授权

US08489907B2 Method of selective power cycling of components in a memory device independently by reducing power to a memory array or memory controller 有权
标题翻译：通过减少存储器阵列或存储器控制器的功率来独立地选择性地对存储器件中的部件进行功率循环的方法
公开(公告)号：US08489907B2
公开(公告)日：2013-07-16
申请号：US12561158
申请日：2009-09-16
申请人： Nir Jacob Wakrat , Anthony Fai , Matthew Byom
发明人： Nir Jacob Wakrat , Anthony Fai , Matthew Byom
IPC分类号： G06F1/00
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/13 , Y02D10/14
摘要： In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.
摘要翻译：在非易失性存储器系统中，物理上分离的电源轨从主机系统提供给NVM设备，用于独立地对NVM设备中的控制器和存储器阵列进行电力循环。 NVM设备的控制器可以通过主机通道向主机系统发送电源循环请求信号，或更新NVM设备中的状态寄存器。主机系统接收并解码电源周期请求信号，或读取状态寄存器，并执行电源循环请求，其中可以包括对NVM设备中的控制器或存储器阵列进行电源循环，或两者兼而有之。功率循环请求可以基于非易失性存储器系统的功率状态，其可以由控制器或主机系统管理，或两者兼而有之。

9. 发明申请

US20130111298A1 SYSTEMS AND METHODS FOR OBTAINING AND USING NONVOLATILE MEMORY HEALTH INFORMATION 审中-公开
标题翻译：用于获取和使用非易失性记忆健康信息的系统和方法
公开(公告)号：US20130111298A1
公开(公告)日：2013-05-02
申请号：US13285145
申请日：2011-10-31
申请人： Nicholas Seroff , Anthony Fai , Nir Jacob Wakrat
发明人： Nicholas Seroff , Anthony Fai , Nir Jacob Wakrat
IPC分类号： H03M13/09 , G06F12/02
CPC分类号： G06F3/0614 , G06F3/064 , G06F3/0679 , G06F11/3034 , G06F11/3055 , G06F11/3409 , G06F11/3485
摘要： Systems and methods are provided for obtaining and using nonvolatile memory (“NVM”) health information. Health information can include a variety of information associated with the performance and reliability of portions of an NVM device, such as the number of errors detected in a portion of NVM or the amount of time required to read from or program a portion of nonvolatile memory. During operation, address specific health information may be stored passively on a host device and provided as part of a command to a memory controller. The memory controller may extract the health information from the command and use the information to execute access requests. After an access request is completed, the memory controller can update the health information and transmit the information back to the host device.
摘要翻译：提供了用于获取和使用非易失性存储器（“NVM”）健康信息的系统和方法。健康信息可以包括与NVM设备的部分的性能和可靠性相关的各种信息，例如在NVM的一部分中检测到的错误的数量或从非易失性存储器的一部分读取或编程所需的时间量。在操作期间，地址特定的健康信息可以在主机设备上被动存储并作为命令的一部分提供给存储器控制器。存储器控制器可以从命令中提取健康信息并使用该信息来执行访问请求。在访问请求完成之后，存储器控制器可以更新健康信息并将信息发送回主机设备。

10. 发明申请

US20130031009A1 AD-HOC CASH DISPENSING NETWORK 审中-公开
标题翻译： AD-HOC现金分配网络
公开(公告)号：US20130031009A1
公开(公告)日：2013-01-31
申请号：US13193546
申请日：2011-07-28
申请人： Arjun Kapoor , Nir Wakrat , Anthony Fai
发明人： Arjun Kapoor , Nir Wakrat , Anthony Fai
IPC分类号： G06Q40/00
CPC分类号： G06Q20/0855 , G06Q20/108 , G06Q20/223 , G06Q20/3223 , G06Q20/3224 , G06Q20/325 , G06Q20/3278 , G06Q20/385 , G06Q30/06 , G06Q40/02
摘要： An ad-hoc cash-dispensing network that allows users to efficiently exchange cash is provided. The ad-hoc cash-dispensing network includes a cash-dispensing server, a network, and a plurality of client terminals that connect to the cash-dispending server through the network. The user of a client terminal sends a request for cash to the cash-dispensing server. The request for cash includes the location of the client terminal. Based on this location, the cash-dispensing server locates one or more other users that are close/proximate to the requesting user and verifies that at least one of these proximate users is willing and able to provide the requested amount of cash. Following the transfer of cash between the parties, the requesting user's account is charged for the service while the providing user's account is credited for the service.
摘要翻译：提供允许用户有效地交换现金的特殊现金分配网络。专用现金分配网络包括通过网络连接到现金支付服务器的现金支出服务器，网络和多个客户终端。客户终端的用户向现金支出服务器发送现金请求。现金请求包括客户终端的位置。基于该位置，现金分配服务器定位一个或多个与请求用户接近/接近的其他用户，并验证这些邻近用户中的至少一个是否愿意并能够提供所请求的金额的现金。在双方之间转移现金后，在提供用户的帐户记入服务时，请求用户的帐户将收取服务费用。

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