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1. 发明申请

US20110066869A1 Memory Array Power Cycling 有权
标题翻译：存储阵列电源循环
公开(公告)号：US20110066869A1
公开(公告)日：2011-03-17
申请号：US12561158
申请日：2009-09-16
申请人： Nir Jacob Wakrat , Anthony Fai , Matthew Byom
发明人： Nir Jacob Wakrat , Anthony Fai , Matthew Byom
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/13 , Y02D10/14
摘要： In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.
摘要翻译：在非易失性存储器系统中，物理上分离的电源轨从主机系统提供给NVM设备，用于独立地对NVM设备中的控制器和存储器阵列进行电力循环。 NVM设备的控制器可以通过主机通道向主机系统发送电源循环请求信号，或更新NVM设备中的状态寄存器。主机系统接收并解码电源周期请求信号，或读取状态寄存器，并执行电源循环请求，其中可以包括对NVM设备中的控制器或存储器阵列进行电源循环，或两者兼而有之。功率循环请求可以基于非易失性存储器系统的功率状态，其可以由控制器或主机系统管理，或两者兼而有之。

2. 发明授权

US08489907B2 Method of selective power cycling of components in a memory device independently by reducing power to a memory array or memory controller 有权
标题翻译：通过减少存储器阵列或存储器控制器的功率来独立地选择性地对存储器件中的部件进行功率循环的方法
公开(公告)号：US08489907B2
公开(公告)日：2013-07-16
申请号：US12561158
申请日：2009-09-16
申请人： Nir Jacob Wakrat , Anthony Fai , Matthew Byom
发明人： Nir Jacob Wakrat , Anthony Fai , Matthew Byom
IPC分类号： G06F1/00
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/13 , Y02D10/14
摘要： In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.
摘要翻译：在非易失性存储器系统中，物理上分离的电源轨从主机系统提供给NVM设备，用于独立地对NVM设备中的控制器和存储器阵列进行电力循环。 NVM设备的控制器可以通过主机通道向主机系统发送电源循环请求信号，或更新NVM设备中的状态寄存器。主机系统接收并解码电源周期请求信号，或读取状态寄存器，并执行电源循环请求，其中可以包括对NVM设备中的控制器或存储器阵列进行电源循环，或两者兼而有之。功率循环请求可以基于非易失性存储器系统的功率状态，其可以由控制器或主机系统管理，或两者兼而有之。

3. 发明授权

US08706955B2 Booting a memory device from a host 有权
标题翻译：从主机启动内存设备
公开(公告)号：US08706955B2
公开(公告)日：2014-04-22
申请号：US13175597
申请日：2011-07-01
申请人： Anthony Fai , Nir Jacob Wakrat , Nicholas Seroff
发明人： Anthony Fai , Nir Jacob Wakrat , Nicholas Seroff
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/0604 , G06F3/0632 , G06F3/0655 , G06F3/0679 , G06F9/4416 , G06F12/0246
摘要： In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory accessible by a controller of the memory device; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, firmware from a host device, wherein the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the firmware from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained through communication with the memory controller of the memory device.
摘要翻译：在一个实现中，一种方法包括在存储器设备处接收引导存储器设备的指令，其中存储器设备包括由存储器设备的控制器可访问的非易失性存储器; 并且响应于接收到引导所述存储器设备的指令，由所述存储器设备从主机设备获得固件，其中所述主机设备与所述存储设备分离并且通信地耦合到所述存储设备。该方法还可以包括使用来自主机设备的固件引导存储设备，其中存储器设备与主机设备分开启动，并且主机设备使用存储在非易失性存储器中的数据或指令来执行操作，并通过与存储器设备的存储器控制器。

4. 发明申请

US20130036255A1 TESTING MEMORY SUBSYSTEM CONNECTIVITY 审中-公开
标题翻译：测试记忆子系统连接
公开(公告)号：US20130036255A1
公开(公告)日：2013-02-07
申请号：US13204074
申请日：2011-08-05
申请人： Anthony Fai , Nir Jacob Wakrat , Nicholas Seroff
发明人： Anthony Fai , Nir Jacob Wakrat , Nicholas Seroff
IPC分类号： G06F12/02
CPC分类号： G06F11/267 , G11C29/08 , G11C2029/0401 , G11C2029/0409
摘要： In one implementation, a memory subsystem includes a plurality of non-volatile memory dies, a memory controller that is communicatively connected to each of the non-volatile memory dies over one or more first busses, a host interface through which the memory controller communicates with a host over a second bus, and a joint test action group (JTAG) interface through which the host performs a boundary scan of the memory subsystem including, at least, the non-volatile memory dies and the memory controller. The memory subsystem can be configured to be a subunit of a board-level memory device that includes the host.
摘要翻译：在一个实现中，存储器子系统包括多个非易失性存储器管芯，存储器控制器，其通过一个或多个第一总线通信地连接到每个非易失性存储器管芯，主机接口，存储器控制器通过该主机接口与通过第二总线的主机，以及联合测试动作组（JTAG）接口，主机执行至少包括非易失性存储器管芯和存储器控制器的存储器子系统的边界扫描。存储器子系统可以被配置为包括主机的电路板级存储器设备的子单元。

5. 发明授权

US08519737B2 Controller interface providing improved signal integrity 有权
标题翻译：控制器接口提供改善的信号完整性
公开(公告)号：US08519737B2
公开(公告)日：2013-08-27
申请号：US13175553
申请日：2011-07-01
申请人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
发明人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
IPC分类号： H03K17/16
CPC分类号： G06F13/4086
摘要： In one implementation, a memory device includes non-volatile memory and a memory controller communicatively coupled to the non-volatile memory over a first bus. The memory device can also include a host device interface through which the memory controller communicates with a host device over a second bus, wherein the host device interface includes an impedance calibration circuit that is adapted to calibrate a signal transmitted over the second bus by host device interface so that a source impedance associated with the signal matches, within a threshold value, a load impedance associated with the host device over the second bus.
摘要翻译：在一个实现中，存储器设备包括非易失性存储器和通过第一总线通信地耦合到非易失性存储器的存储器控制器。存储器设备还可以包括主机设备接口，存储器控制器通过该主机设备接口通过第二总线与主机设备进行通信，其中主机设备接口包括阻抗校准电路，该阻抗校准电路适于通过主机设备校准在第二总线上发送的信号接口，使得与该信号相关联的源阻抗在阈值内匹配通过第二总线与主机设备相关联的负载阻抗。

6. 发明授权

US08472274B2 Using temperature sensors with a memory device 有权
标题翻译：使用具有存储器件的温度传感器
公开(公告)号：US08472274B2
公开(公告)日：2013-06-25
申请号：US13038860
申请日：2011-03-02
申请人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
发明人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
IPC分类号： G11C7/04 , G11C11/56
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/26
摘要： In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells. The method can further include reading, by the memory device, the data from the non-volatile memory cells. The method can also include processing the read data based on, at least, the retrieved temperature information; and providing the processed data.
摘要翻译：在一个实现中，用于执行存储器操作的方法包括在存储器设备处接收从一个或多个非易失性存储器单元读取数据的请求; 以及检索与所述非易失性存储器单元相关联的存储的温度信息，其中所述温度信息与所述数据被写入所述非易失性存储器单元时的大致时间相关联。该方法还可以包括由存储器件读取来自非易失性存储器单元的数据。该方法还可以包括至少基于检索到的温度信息来处理读取的数据; 并提供处理的数据。

7. 发明授权

US10359949B2 Systems and methods for obtaining and using nonvolatile memory health information 有权
公开(公告)号：US10359949B2
公开(公告)日：2019-07-23
申请号：US13285145
申请日：2011-10-31
申请人： Nicholas Seroff , Anthony Fai , Nir Jacob Wakrat
发明人： Nicholas Seroff , Anthony Fai , Nir Jacob Wakrat
IPC分类号： G11C29/00 , G06F3/06 , G06F11/30 , G06F11/34
摘要： Systems and methods are provided for obtaining and using nonvolatile memory (“NVM”) health information. Health information can include a variety of information associated with the performance and reliability of portions of an NVM device, such as the number of errors detected in a portion of NVM or the amount of time required to read from or program a portion of nonvolatile memory. During operation, address specific health information may be stored passively on a host device and provided as part of a command to a memory controller. The memory controller may extract the health information from the command and use the information to execute access requests. After an access request is completed, the memory controller can update the health information and transmit the information back to the host device.

8. 发明授权

US08966319B2 Obtaining debug information from a flash memory device 有权
标题翻译：从闪存设备获取调试信息
公开(公告)号：US08966319B2
公开(公告)日：2015-02-24
申请号：US13032541
申请日：2011-02-22
申请人： Anthony Fai , Nir Jacob Wakrat , Nicholas Seroff
发明人： Anthony Fai , Nir Jacob Wakrat , Nicholas Seroff
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/362
摘要： This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.
摘要翻译：本文档通常描述了用于从存储器设备获取调试信息的系统，设备，方法和技术。调试信息可以包括与可以用于调试设备的存储器设备相关联的各种信息，诸如由存储器件执行的操作序列和关于发生的错误的信息（例如，错误的类型，存储器的组件设备与错误相关）。主机可以指示存储器设备来获取并向主机提供调试信息。存储器设备可以被配置为使用诸如触发器的各种特征来获得特定的调试信息。例如，存储器件可以使用触发器来收集与失败的擦除操作有关的调试信息。

9. 发明授权

US08880779B2 Debugging a memory subsystem 有权
标题翻译：调试内存子系统
公开(公告)号：US08880779B2
公开(公告)日：2014-11-04
申请号：US13204037
申请日：2011-08-05
申请人： Anthony Fai , Nir Jacob Wakrat , Nicholas Seroff
发明人： Anthony Fai , Nir Jacob Wakrat , Nicholas Seroff
IPC分类号： G06F12/02 , G06F11/263
CPC分类号： G06F11/263
摘要： In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.
摘要翻译：在一个实现中，存储器子系统包括非易失性存储器，通过第一总线通信地连接到非易失性存储器的存储器控制器，存储器控制器经由第二总线与主机控制器通信的主机接口，以及联合测试动作组（JTAG）接口，为主机控制器提供与存储器控制器相关联的状态信息的访问。存储器子系统可以被配置为耦合到包括主机控制器的电路板级存储器设备。

10. 发明授权

US08713404B2 Controller interface providing improved data reliability 失效
标题翻译：控制器接口提供更好的数据可靠性
公开(公告)号：US08713404B2
公开(公告)日：2014-04-29
申请号：US13175610
申请日：2011-07-01
申请人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
发明人： Anthony Fai , Nicholas Seroff , Nir Jacob Wakrat
IPC分类号： G11C29/00 , H04L1/18 , H03M13/00 , G01V3/00 , G01R31/00 , G11C11/34 , G11C16/04
CPC分类号： G06F11/1004
摘要： In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.
摘要翻译：在一个实现中，存储器设备包括非易失性存储器，通过第一总线通信地耦合到非易失性存储器的存储器控制器以及存储器控制器经由第二总线与主机设备通信的主机接口。存储器装置还可以包括主机接口的信号调节器，其适于根据从主机设备接收的信号电平数据调节信号以调整在第二总线上接收的信号的信号电平，其中信号电平数据与电压电平相关的由主机设备生成的信号，以对通过第二总线发送的数据进行编码。

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