专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100085086A1 Digital Frequency Detector 审中-公开
标题翻译：数字频率检测器
公开(公告)号：US20100085086A1
公开(公告)日：2010-04-08
申请号：US12510211
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
IPC分类号： H03B19/00
CPC分类号： H03L7/091 , H03L7/099 , H03L7/10 , H03L2207/06 , H04L7/033
摘要： In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values.
摘要翻译：在一个实施例中，描述了一种包括接收第一时钟信号和第二时钟信号的方法; 将第一时钟信号除以n的值以产生分割的第一时钟信号; 对所述分频的第一时钟信号与所述第二时钟信号对所述频率检测器进行采样以产生多个采样; 如果一组连续样本中多于一个预定数量的连续样本具有相同的逻辑值，则产生第一调整信号; 以及如果小于所述连续样本集合中的预定数量的连续样本具有相同的逻辑值，则产生第二调整信号。

2. 发明申请

US20100090733A1 Generating Multiple Clock Phases 有权
标题翻译：生成多个时钟相位
公开(公告)号：US20100090733A1
公开(公告)日：2010-04-15
申请号：US12511352
申请日：2009-07-29
申请人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
发明人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。

3. 发明授权

US08058914B2 Generating multiple clock phases 有权
标题翻译：生成多个时钟阶段
公开(公告)号：US08058914B2
公开(公告)日：2011-11-15
申请号：US12511352
申请日：2009-07-29
申请人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
发明人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。

4. 发明授权

US08718217B2 Clock and data recovery (CDR) using phase interpolation 有权
标题翻译：时钟和数据恢复（CDR）使用相位插值
公开(公告)号：US08718217B2
公开(公告)日：2014-05-06
申请号：US12511365
申请日：2009-07-29
申请人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
发明人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
IPC分类号： H03D3/24
CPC分类号： H03L7/091 , H03L7/087 , H03L7/0998
摘要： In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.
摘要翻译：在一个实施例中，电路包括被配置为产生k个第一时钟信号的压控振荡器（VCO），每个第一时钟信号各自具有基于电荷泵控制电压信号的第一相位; 配置成接收k个第一时钟信号的一个或多个相位内插器（PI）和一个或多个第一反馈控制信号并产生m个第二时钟信号，每个第二时钟信号基于k个第一时钟信号和一个或多个第一反馈控制信号; 第一相位检测器（PD），被配置为接收m个第二时钟信号，并且基于m个第二时钟信号产生一个或多个第一反馈控制信号; 配置为基于所述m个第二时钟信号产生一个或多个第二反馈控制信号的第二PD; 以及电荷泵，被配置为基于所述第二反馈控制信号输出所述电荷泵控制电压信号。

5. 发明授权

US08300754B2 Clock and data recovery with a data aligner 有权
标题翻译：使用数据对准器进行时钟和数据恢复
公开(公告)号：US08300754B2
公开(公告)日：2012-10-30
申请号：US12510199
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
IPC分类号： H04L7/00
CPC分类号： H04J3/0685 , H03M9/00
摘要： In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.
摘要翻译：在一个实施例中，一种方法包括分别接收包括第一和第二输入数据位的第一和第二输入流。该方法包括分别基于第一和第二输入流产生第一和第二恢复时钟。该方法包括对第一和第二输入数据位进行重新定时和解复用以分别产生n个第一恢复流和n个第二恢复流，每个包括第一和第二恢复数据位。该方法还包括确定第一和第二恢复时钟之间的相位差; 至少部分地基于n的值和相位差将第一恢复数据位与第二恢复数据位对准; 组合第一和第二恢复数据比特以产生输出流; 以及基于所述第一恢复时钟或第二恢复时钟重新计时输出流中的第一和第二恢复数据比特。

6. 发明申请

US20100104057A1 Clock and Data Recovery with a Data Aligner 有权
标题翻译：使用数据对齐器进行时钟和数据恢复
公开(公告)号：US20100104057A1
公开(公告)日：2010-04-29
申请号：US12510199
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
IPC分类号： H04L7/02
CPC分类号： H04J3/0685 , H03M9/00
摘要： In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.
摘要翻译：在一个实施例中，一种方法包括分别接收包括第一和第二输入数据位的第一和第二输入流。该方法包括分别基于第一和第二输入流产生第一和第二恢复时钟。该方法包括对第一和第二输入数据位进行重新定时和解复用以分别产生n个第一恢复流和n个第二恢复流，每个包括第一和第二恢复数据位。该方法还包括确定第一和第二恢复时钟之间的相位差; 至少部分地基于n的值和相位差将第一恢复数据位与第二恢复数据位对准; 组合第一和第二恢复数据比特以产生输出流; 以及基于所述第一恢复时钟或第二恢复时钟重新计时输出流中的第一和第二恢复数据比特。

7. 发明授权

US08300753B2 Triple loop clock and data recovery (CDR) 有权
标题翻译：三回路时钟和数据恢复（CDR）
公开(公告)号：US08300753B2
公开(公告)日：2012-10-30
申请号：US12510160
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0891 , H03L7/091 , H03L7/113 , H04L7/0004
摘要： In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.
摘要翻译：在一个实施例中，一种方法包括访问具有参考时钟频率和参考时钟相位的参考时钟; 产生具有作为模拟控制电压设定和频率增益曲线的函数的输出时钟相位和输出时钟频率的输出时钟; 将模拟控制电压设置固定为预定电压; 在模拟控制电压设定下，在参考时钟频率的预定频率范围内选择一个频率增益曲线; 调整所述模拟控制电压设定以将所述输出时钟频率调整到所述参考时钟频率的另一预定频率范围内; 以及将输出时钟相位调整在输入数据流的输入数据相位的预定相位范围内。

8. 发明申请

US20100091927A1 Clock and Data Recovery (CDR) Using Phase Interpolation 有权
标题翻译：时钟和数据恢复（CDR）使用相位插值
公开(公告)号：US20100091927A1
公开(公告)日：2010-04-15
申请号：US12511365
申请日：2009-07-29
申请人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
发明人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
IPC分类号： H04L27/01
CPC分类号： H03L7/091 , H03L7/087 , H03L7/0998
摘要： In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.
摘要翻译：在一个实施例中，电路包括被配置为产生k个第一时钟信号的压控振荡器（VCO），每个第一时钟信号各自具有基于电荷泵控制电压信号的第一相位; 配置成接收k个第一时钟信号的一个或多个相位内插器（PI）和一个或多个第一反馈控制信号并产生m个第二时钟信号，每个第二时钟信号基于k个第一时钟信号和一个或多个第一反馈控制信号; 第一相位检测器（PD），被配置为接收m个第二时钟信号，并且基于m个第二时钟信号产生一个或多个第一反馈控制信号; 配置为基于所述m个第二时钟信号产生一个或多个第二反馈控制信号的第二PD; 以及电荷泵，被配置为基于所述第二反馈控制信号输出所述电荷泵控制电压信号。

9. 发明申请

US20100091925A1 Triple Loop Clock and Data Recovery (CDR) 有权
标题翻译：三回路时钟和数据恢复（CDR）
公开(公告)号：US20100091925A1
公开(公告)日：2010-04-15
申请号：US12510160
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
IPC分类号： H04L7/02
CPC分类号： H04L7/033 , H03L7/0891 , H03L7/091 , H03L7/113 , H04L7/0004
摘要： In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.
摘要翻译：在一个实施例中，一种方法包括访问具有参考时钟频率和参考时钟相位的参考时钟; 产生具有作为模拟控制电压设定和频率增益曲线的函数的输出时钟相位和输出时钟频率的输出时钟; 将模拟控制电压设置固定为预定电压; 在模拟控制电压设定下，在参考时钟频率的预定频率范围内选择一个频率增益曲线; 调整所述模拟控制电压设定以将所述输出时钟频率调整到所述参考时钟频率的另一预定频率范围内; 以及将输出时钟相位调整在输入数据流的输入数据相位的预定相位范围内。

10. 发明授权

US07405593B2 Systems and methods for transmitting signals across integrated circuit chips 有权
标题翻译：跨集成电路芯片传输信号的系统和方法
公开(公告)号：US07405593B2
公开(公告)日：2008-07-29
申请号：US11265550
申请日：2005-11-01
申请人： Nestor Tzartzanis , William W. Walker
发明人： Nestor Tzartzanis , William W. Walker
IPC分类号： H03K19/094
CPC分类号： H04L25/0282 , H03K3/356191 , H03K3/35625 , H04L25/0272 , H04L25/0294 , Y10T83/2037 , Y10T83/204
摘要： Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.
摘要翻译：本发明公开了采用差分电流模式感测的片上全球电信令系统和方法，与传统的逆变器中继器相比具有降低的延迟和能量消耗。本发明可以用于点到点连接以及N到1连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式