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1. 发明申请

US20100090733A1 Generating Multiple Clock Phases 有权
标题翻译：生成多个时钟相位
公开(公告)号：US20100090733A1
公开(公告)日：2010-04-15
申请号：US12511352
申请日：2009-07-29
申请人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
发明人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。

2. 发明授权

US08058914B2 Generating multiple clock phases 有权
标题翻译：生成多个时钟阶段
公开(公告)号：US08058914B2
公开(公告)日：2011-11-15
申请号：US12511352
申请日：2009-07-29
申请人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
发明人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。

3. 发明授权

US08718217B2 Clock and data recovery (CDR) using phase interpolation 有权
标题翻译：时钟和数据恢复（CDR）使用相位插值
公开(公告)号：US08718217B2
公开(公告)日：2014-05-06
申请号：US12511365
申请日：2009-07-29
申请人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
发明人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
IPC分类号： H03D3/24
CPC分类号： H03L7/091 , H03L7/087 , H03L7/0998
摘要： In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.
摘要翻译：在一个实施例中，电路包括被配置为产生k个第一时钟信号的压控振荡器（VCO），每个第一时钟信号各自具有基于电荷泵控制电压信号的第一相位; 配置成接收k个第一时钟信号的一个或多个相位内插器（PI）和一个或多个第一反馈控制信号并产生m个第二时钟信号，每个第二时钟信号基于k个第一时钟信号和一个或多个第一反馈控制信号; 第一相位检测器（PD），被配置为接收m个第二时钟信号，并且基于m个第二时钟信号产生一个或多个第一反馈控制信号; 配置为基于所述m个第二时钟信号产生一个或多个第二反馈控制信号的第二PD; 以及电荷泵，被配置为基于所述第二反馈控制信号输出所述电荷泵控制电压信号。

4. 发明申请

US20100091927A1 Clock and Data Recovery (CDR) Using Phase Interpolation 有权
标题翻译：时钟和数据恢复（CDR）使用相位插值
公开(公告)号：US20100091927A1
公开(公告)日：2010-04-15
申请号：US12511365
申请日：2009-07-29
申请人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
发明人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
IPC分类号： H04L27/01
CPC分类号： H03L7/091 , H03L7/087 , H03L7/0998
摘要： In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.
摘要翻译：在一个实施例中，电路包括被配置为产生k个第一时钟信号的压控振荡器（VCO），每个第一时钟信号各自具有基于电荷泵控制电压信号的第一相位; 配置成接收k个第一时钟信号的一个或多个相位内插器（PI）和一个或多个第一反馈控制信号并产生m个第二时钟信号，每个第二时钟信号基于k个第一时钟信号和一个或多个第一反馈控制信号; 第一相位检测器（PD），被配置为接收m个第二时钟信号，并且基于m个第二时钟信号产生一个或多个第一反馈控制信号; 配置为基于所述m个第二时钟信号产生一个或多个第二反馈控制信号的第二PD; 以及电荷泵，被配置为基于所述第二反馈控制信号输出所述电荷泵控制电压信号。

5. 发明授权

US08138798B2 Symmetric phase detector 失效
标题翻译：对称相位检测器
公开(公告)号：US08138798B2
公开(公告)日：2012-03-20
申请号：US12511340
申请日：2009-07-29
申请人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
发明人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03D13/008 , H03L7/085 , H03L7/089
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一输入信号的第一电路输入端; 用于接收具有第二相位的第二输入信号的第二电路输入; 用于输出电路输出信号的电路输出; 第一混频器单元，包括第一混频器单元输入，第二混频器单元输入和第一混频器单元输出; 以及包括第三混频器单元输入，第四混频器单元输入和第二混频器单元输出的第二混频器单元。第一电路输入连接到第一和第二混频器单元输入，第二电路输入连接到第二和第四混频器单元输入，并且组合第一和第二混频器单元输出以提供电路输出。电路输出信号的电流与第一和第二相之间的相位偏移成比例。

6. 发明申请

US20120177162A1 Symmetric Phase Detector 审中-公开
标题翻译：对称相位检测器
公开(公告)号：US20120177162A1
公开(公告)日：2012-07-12
申请号：US13424728
申请日：2012-03-20
申请人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
发明人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
IPC分类号： H04L27/06 , H03D13/00
CPC分类号： H03D13/008 , H03L7/085 , H03L7/089
摘要： In one embodiment, a circuit includes a first mixer cell and a second mixer cell that each have respectively a first cell input, a second cell input, and a cell output. The circuit includes a first circuit input configured to receive a first input signal having a first phase. The first circuit input is connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell. The circuit includes a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value. The second circuit input is connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell.
摘要翻译：在一个实施例中，电路包括分别具有第一单元输入，第二单元输入和单元输出的第一混频器单元和第二混频器单元。电路包括被配置为接收具有第一相位的第一输入信号的第一电路输入。第一电路输入连接到第一混频器单元的第一单元输入和第二混频器单元的第二单元输入。电路包括第二电路输入，其配置为接收具有与第一相分离的第二相位的标称值的第二输入信号。第二电路输入连接到第一混频器单元的第二单元输入和第二混频器单元的第一单元输入。

7. 发明申请

US20100090723A1 Symmetric Phase Detector 失效
标题翻译：对称相位检测器
公开(公告)号：US20100090723A1
公开(公告)日：2010-04-15
申请号：US12511340
申请日：2009-07-29
申请人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
发明人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
IPC分类号： H03D13/00
CPC分类号： H03D13/008 , H03L7/085 , H03L7/089
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一输入信号的第一电路输入端; 用于接收具有第二相位的第二输入信号的第二电路输入; 用于输出电路输出信号的电路输出; 第一混频器单元，包括第一混频器单元输入，第二混频器单元输入和第一混频器单元输出; 以及包括第三混频器单元输入，第四混频器单元输入和第二混频器单元输出的第二混频器单元。第一电路输入连接到第一和第二混频器单元输入，第二电路输入连接到第二和第四混频器单元输入，并且组合第一和第二混频器单元输出以提供电路输出。电路输出信号的电流与第一和第二相之间的相位偏移成比例。

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