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    • 1. 发明授权
    • Method and system for reading data from and writing data to a memory
    • 从数据读取和写入数据到存储器的方法和系统
    • US06986012B2
    • 2006-01-10
    • US10233450
    • 2002-09-03
    • Hong LiNicolaas LambertRobert JochemsenRudi Jozef Marie WijnandsOzcan Mesut
    • Hong LiNicolaas LambertRobert JochemsenRudi Jozef Marie WijnandsOzcan Mesut
    • G06F12/00
    • G11B20/10527G06F3/061G06F3/0619G06F3/0659G06F3/0676G06F11/00
    • The invention relates to a method of writing data to and reading data from a memory (102) by a host. By limiting processing time, time restrictions regarding the data to be processed can be met. However, this is at the expense of data integrity. By setting time limits for a group (300) of multiple processing assignments and dynamic allocation of time, reserved for error recovery and retries, data integrity can be improved, while time limits can still be met. Furthermore, by attaching priorities to the assignments, multiple types of data can be handled in one group of assignments. For example, assignments with real-time requirements can be put in a group with assignments with best effort requirements. In this way, more flexible planning of processing assignments is possible. The invention also relates to a system for writing data to and reading data from a memory.
    • 本发明涉及一种向主机向存储器(102)写入数据并从其读取数据的方法。 通过限制处理时间,可以满足关于要处理的数据的时间限制。 但是,这是牺牲数据完整性。 通过为多个处理分配的组(300)设置时间限制和动态分配时间,保留用于错误恢复和重试,可以提高数据完整性,同时可以满足时间限制。 此外,通过将优先级附加到分配,可以在一组分配中处理多种类型的数据。 例如,具有实时要求的分配可以放在具有尽力而为要求的分配的组中。 以这种方式,可以进行更灵活的处理分配计划。 本发明还涉及一种用于将数据写入和从存储器读取数据的系统。
    • 6. 发明授权
    • Circuit with a memory array and a reference level generator circuit
    • 具有存储器阵列和参考电平发生器电路的电路
    • US08081523B2
    • 2011-12-20
    • US11813862
    • 2006-01-05
    • Victor Martinus Van AchtNicolaas LambertPierre Hermanus Woerlee
    • Victor Martinus Van AchtNicolaas LambertPierre Hermanus Woerlee
    • G11C5/14
    • G11C7/14
    • A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi-level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.
    • 电路包括存储器单元阵列(10)。 多个感测电路(20)耦合到相应存储单元(10)的输出(14),用于将存储单元(10)中的相应一个的输出信号与参考信号进行比较以形成数据信号 来自存储单元(10)中的相应一个的输出信号。 参考发生器电路(24,26)从一个和形成参考信号,其中寻址组的每个存储单元(10)中的每个相应的一个贡献作为存储单元的相应一个的输出信号的函数 (10)。 在超过参考信号的饱和距离上的输出信号值的贡献相等,并且在超过参考信号以下的饱和距离处的输出信号值的贡献相等。 在单元格中存储多级数据的情况下,从基准电平以上和低于基准电平的中心电平到饱和电平的距离是相互不同的,其比率对应于已经被编程的单元计数的比率 各级别。
    • 8. 发明授权
    • Universal memory device having a profile storage unit
    • 具有简档存储单元的通用存储器件
    • US07831790B2
    • 2010-11-09
    • US10549367
    • 2004-03-17
    • Nicolaas LambertAdrianus Johannes Maria DenissenWilhelmus Franciscus Johannes FontijnRobert Jochemsen
    • Nicolaas LambertAdrianus Johannes Maria DenissenWilhelmus Franciscus Johannes FontijnRobert Jochemsen
    • G06F13/10
    • G06F21/78G06F21/79G06F2221/2141G11C7/1045G11C7/24G11C16/22
    • A universal memory device is presented that provides adaptability to existing hardware and software environments. The memory can “mimic” existing memory technology combining the advantages of integrating all memory capacity into one single technology and still providing the implicit protections and access characteristics known from the different existing memory technologies. The memory device comprises a memory having low-latency, rewritable, non-volatile memory cells, a profile storage unit connected with the memory and comprising access information allocated to a set of request information elements (request profile), such that the access information indicates whether an access request to said memory, the access request having the request profile, is to be allowed or rejected, and an access control unit communicating with the profile storage unit and the memory, and adapted to allow or reject an incoming access request in dependence on the access information allocated to the request profile of the access request.
    • 提出了一种提供对现有硬件和软件环境的适应性的通用存储器件。 存储器可以“模拟”现有存储器技术,结合将所有存储器容量集成到一个单一技术中并且仍然提供从不同现有存储器技术已知的隐式保护和访问特性的优点。 存储装置包括具有低等待时间,可重写,非易失性存储器单元的存储器,与存储器连接的简档存储单元,并且包括分配给一组请求信息元素(请求简档)的访问信息,使得访问信息指示 是否允许或拒绝对所述存储器的访问请求,具有请求简档的访问请求,以及与简档存储单元和存储器通信的访问控制单元,并且适于依赖于允许或拒绝传入的访问请求 关于分配给访问请求的请求简档的访问信息。
    • 10. 发明申请
    • ELECTRONIC CIRCUIT THAT COMPRISES A MEMORY MATRIX AND METHOD OF READING FOR BITLINE NOISE COMPENSATION
    • 包含记忆矩阵的电子电路和用于BITLINE噪声补偿的读取方法
    • US20100232245A1
    • 2010-09-16
    • US12293817
    • 2007-03-27
    • Victor M. G. Van AchtNicolaas Lambert
    • Victor M. G. Van AchtNicolaas Lambert
    • G11C7/02
    • G11C7/02G11C7/062G11C7/14G11C7/18
    • Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).
    • 从具有多个位线(12)的存储矩阵(10)中读取数据。 差分读出放大器(14)在第一输入端接收从位线(12)中的第一位导出的信号。 差分读出放大器(14)从参考电路(15)的参考输出接收参考信号到第二输入端。 与位线(12)中的第一位相邻的位线(12)中的第二位被耦合到参考电路(15),使得位的第二位上的位线信号值 行(12)影响参考输出上的参考信号值,至少部分地再现位线信号值(12)上的位线信号值(12)对第二位线(12)上的串扰的影响 第一个位线(12)。