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1. 发明申请

US20050071518A1 Flag value renaming 审中-公开
标题翻译：标志值重命名
公开(公告)号：US20050071518A1
公开(公告)日：2005-03-31
申请号：US10677039
申请日：2003-09-30
申请人： Nicholas Samra , Stephan Jourdan , Jonathan Combs , Avinash Sodani , Per Hammarlund , Michael Cornaby
发明人： Nicholas Samra , Stephan Jourdan , Jonathan Combs , Avinash Sodani , Per Hammarlund , Michael Cornaby
IPC分类号： G06F3/00 , G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： According to an embodiment of the invention, a method and apparatus for flag value renaming. An embodiment of a method comprises setting a flag for a processor via a first instruction, the first instruction being either a direct update instruction or an indirect update instruction; if the setting of the flag is by a direct update instruction, executing a succeeding second instruction that reads the flag prior to completion of the first instruction; and if the setting of the flag is by an indirect update instruction, delaying the second instruction until after completion of the first instruction.
摘要翻译：根据本发明的实施例，一种用于标志值重命名的方法和装置。方法的实施例包括经由第一指令设置处理器的标志，第一指令是直接更新指令或间接更新指令; 如果所述标志的设置是通过直接更新指令，则执行在完成所述第一指令之前读取所述标志的后续第二指令; 并且如果所述标志的设置是通过间接更新指令，则延迟所述第二指令直到所述第一指令完成为止。

2. 发明申请

US20060123219A1 Intra-instruction fusion 审中-公开
标题翻译：指令内融合
公开(公告)号：US20060123219A1
公开(公告)日：2006-06-08
申请号：US11339019
申请日：2006-01-24
申请人： Nicholas Samra , Stephan Jourdan
发明人： Nicholas Samra , Stephan Jourdan
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/3853
摘要： Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.
摘要翻译：将微操作（uops）融合在一起。内部指令融合可以在微处理器内提高高速缓冲存储器存储效率和计算机指令处理带宽，而不会导致重大的计算机系统成本。 Uops被融合，存储在缓存中，未融合，并行执行并退出，以优化成本和性能。

3. 发明授权

US06907518B1 Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same 有权
标题翻译：具有无序执行能力的流水线，超标量浮点单元和采用该程序的处理器
公开(公告)号：US06907518B1
公开(公告)日：2005-06-14
申请号：US10462585
申请日：2003-06-16
申请人： Jeffrey Lohman , Nicholas Samra , Ram Gummadi
发明人： Jeffrey Lohman , Nicholas Samra , Ram Gummadi
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/3001 , G06F9/3012 , G06F9/3013 , G06F9/30134 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3875
摘要： For use in a processor having a first number of decode units for decoding an ordered stream of floating point instructions, a floating point unit (FPU) for receiving decoded ones of the floating point instructions and a method of processing the decoded ones of the floating point instructions. In one embodiment, the FPU includes: (1) a second number of floating point pipelines that execute the floating point instructions, the second number being at least one and less than the first number, the floating point pipeline having a load unit, an execution core and a store unit, (2) a floating point checkpoint buffer, coupled to the decode units, that queues the decoded ones of the floating point instructions for allocation to the floating point pipelines and (3) a floating point register file, coupled to and cooperable with the floating point checkpoint buffer, that preserves states of the execution core to allow the floating point pipelines to execute the floating point instructions out of order.
摘要翻译：为了在具有用于解码浮点指令的有序流的第一数量的解码单元的处理器中使用用于接收浮点指令的解码的浮点指令的浮点单元（FPU），以及处理浮点的解码单元说明。在一个实施例中，FPU包括：（1）执行浮点指令的第二数量的浮点流水线，第二数量至少为第一数量，并且小于第一数量，浮点流水线具有负载单元，执行核心和存储单元，（2）耦合到解码单元的浮点检查点缓冲器，对解码的浮点指令进行排队以分配给浮点流水线;以及（3）浮点寄存器堆，耦合到并与浮点检查点缓冲区配合，保留执行核心的状态，以允许浮点管道按顺序执行浮点指令。

4. 发明申请

US20050228971A1 Buffer virtualization 审中-公开
标题翻译：缓冲区虚拟化
公开(公告)号：US20050228971A1
公开(公告)日：2005-10-13
申请号：US10821309
申请日：2004-04-08
申请人： Nicholas Samra , Belliappa Kuttanna , Rajesh Patel
发明人： Nicholas Samra , Belliappa Kuttanna , Rajesh Patel
IPC分类号： G06F9/26 , G06F9/50
CPC分类号： G06F9/5016
摘要： A buffer virtualization mechanism to allow for a large number of allocate-able buffering resources. In particular, embodiments of the invention involve a tracking technique for implementing the use of virtual buffers within a microprocessor architecture.
摘要翻译：缓冲区虚拟化机制，允许大量可分配的缓冲资源。特别地，本发明的实施例涉及用于在微处理器架构内实现虚拟缓冲器的使用的跟踪技术。

5. 发明申请

US20050149700A1 Virtual multithreading translation mechanism including retrofit capability 失效
标题翻译：虚拟多线程翻译机制，包括改进能力
公开(公告)号：US20050149700A1
公开(公告)日：2005-07-07
申请号：US10741914
申请日：2003-12-19
申请人： Nicholas Samra , Andrew Huang
发明人： Nicholas Samra , Andrew Huang
IPC分类号： G06F7/38 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/3851
摘要： Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A thread translation table maintains physical-to-virtual thread translation information in order to provide such information to structures within a processor that utilize virtual thread information. By associating a thread translation table with such structures, a processor that supports simultaneous multithreading (SMT) may be easily retrofitted to support switch-on-event multithreading on the SMT logical processors.
摘要翻译：方法，装置和系统实施例提供对多个SMT逻辑线程上下文上的多个SoEMT软件线程的支持。线程转换表维护物理到虚拟线程转换信息，以便向利用虚拟线程信息的处理器内的结构提供这样的信息。通过将线程转换表与这种结构相关联，支持同时多线程（SMT）的处理器可以轻松地被改进以支持SMT逻辑处理器上的事件开启事务多线程。

6. 发明授权

US06581155B1 Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same 有权
标题翻译：具有无序执行能力的流水线，超标量浮点单元和采用该程序的处理器
公开(公告)号：US06581155B1
公开(公告)日：2003-06-17
申请号：US09382898
申请日：1999-08-25
申请人： Jeffrey Lohman , Nicholas Samra , Ram Gummadi
发明人： Jeffrey Lohman , Nicholas Samra , Ram Gummadi
IPC分类号： G06F9302
CPC分类号： G06F9/3822 , G06F9/3001 , G06F9/3012 , G06F9/3013 , G06F9/30134 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3875
摘要： For use in a processor having a first number of decode units for decoding an ordered stream of floating point instructions, a floating point unit (FPU) for receiving decoded ones of the floating point instructions and a method of processing the decoded ones of the floating point instructions. In one embodiment, the FPU includes: (1) a second number of floating point pipelines that execute the floating point instructions, the second number being at least one and less than the first number, the floating point pipeline having a load unit, an execution core and a store unit, (2) a floating point checkpoint buffer, coupled to the decode units, that queues the decoded ones of the floating point instructions for allocation to the floating point pipelines and (3) a floating point register file, coupled to and cooperable with the floating point checkpoint buffer, that preserves states of the execution core to allow the floating point pipelines to execute the floating point instructions out of order.
摘要翻译：为了在具有用于解码浮点指令的有序流的第一数量的解码单元的处理器中使用用于接收浮点指令的解码的浮点指令的浮点单元（FPU），以及处理浮点的解码单元说明。在一个实施例中，FPU包括：（1）执行浮点指令的第二数量的浮点流水线，第二数量至少为第一数量，并且小于第一数量，浮点流水线具有负载单元，执行核心和存储单元，（2）耦合到解码单元的浮点检查点缓冲器，对解码的浮点指令进行排队以分配给浮点流水线;以及（3）浮点寄存器堆，耦合到并与浮点检查点缓冲区配合，保留执行核心的状态，以允许浮点管道按顺序执行浮点指令。

7. 发明授权

US5448722A Method and system for data processing system error diagnosis utilizing hierarchical blackboard diagnostic sessions 失效
标题翻译：利用分层黑板诊断会话的数据处理系统错误诊断方法和系统
公开(公告)号：US5448722A
公开(公告)日：1995-09-05
申请号：US29072
申请日：1993-03-10
申请人： Kenton J. Lynne , Nicholas Samra , Thomas M. Walker
发明人： Kenton J. Lynne , Nicholas Samra , Thomas M. Walker
IPC分类号： G06F11/22 , G06F11/00
CPC分类号： G06F11/2273 , Y10S706/916
摘要： A method and system in a data processing system for managing a hierarchical error diagnostic system having a plurality of diagnostic modules for diagnosing a component failure within a target system having a predetermined group of components within each of a plurality of hierarchical levels. After the identification of selected hierarchical levels within the target system, and identification of the components within each hierarchical level, a first blackboard data storage area is initialized for utilization during a diagnostic session. Thereafter, a diagnostic analysis of a first predetermined group of components within a first selected hierarchical level is initiated. The diagnostic analysis utilizes the first blackboard data storage area and multiple diagnostic modules assigned to diagnose the components within the first selected hierarchical level. Upon conclusion of the diagnostic analysis, a diagnostic result is determined from selected information learned during the first diagnostic analysis. In preparation for a second diagnostic analysis of a second group of components in a second hierarchical level, which were selected in response to a result from the initial diagnostic analysis, a second blackboard data storage area is initialized utilizing selected information learned from the initial diagnostic analysis. Thereafter, a second diagnostic analysis of a second predetermined group of components within a second selected hierarchical level is automatically initiated. The second diagnostic analysis utilizes selected information learned during the initial diagnostic session, which is stored within the second blackboard data storage area during initialization, and multiple diagnostic modules within the second selected hierarchical level.
摘要翻译：一种数据处理系统中的方法和系统，用于管理具有多个诊断模块的分层错误诊断系统，所述多个诊断模块用于诊断目标系统内的组件故障，所述目标系统具有多个分级级别内的每一个中的预定组分组。在目标系统中选择的分层级别的识别以及每个分层级别内的组件的标识之后，初始化第一黑板数据存储区域以便在诊断会话期间利用。此后，启动对第一选定分层级内的第一预定组分组的诊断分析。诊断分析利用第一个黑板数据存储区域和多个分配诊断模块来诊断第一个选择的层级中的组件。诊断分析结束后，从第一次诊断分析期间所选择的信息中确定诊断结果。为了准备对响应于初始诊断分析的结果而选择的第二层次中的第二组组件的第二诊断分析，使用从初始诊断分析获得的所选信息来初始化第二黑板数据存储区域。此后，自动启动在第二选择分层级内的第二预定组分组的第二诊断分析。第二诊断分析利用在初始诊断期间学习的所选信息，其在初始化期间存储在第二黑板数据存储区域内，以及在第二选择分层级别内的多个诊断模块。

8. 发明申请

US20070234094A1 METHODS AND APPARATUS TO CONTROL POWER CONSUMPTION WITHIN A PROCESSOR 有权
标题翻译：在处理器中控制消耗电力的方法和装置
公开(公告)号：US20070234094A1
公开(公告)日：2007-10-04
申请号：US11759776
申请日：2007-06-07
申请人： Nicholas Samra , Andrew Huang , Namratha Jaisimha
发明人： Nicholas Samra , Andrew Huang , Namratha Jaisimha
IPC分类号： G06F1/18
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3885 , G06F9/3891 , Y02D10/128 , Y02D10/171
摘要： Methods and apparatus are disclosed to control power consumption within a processor. An example apparatus disclosed herein includes logic to identify at least one instruction type and to initialize a counter value corresponding to a maximum number of instructions to be performed, the maximum number being at least partially dependent upon the identified at least one instruction type. The example apparatus also includes processing logic to be enabled or disabled based, at least in part, on the counter value.
摘要翻译：公开了用于控制处理器内的功率消耗的方法和装置。这里公开的示例性装置包括用于识别至少一种指令类型并初始化与要执行的指令的最大数量相对应的计数器值的逻辑，最大数量至少部分取决于所识别的至少一种指令类型。至少部分地基于计数器值，示例性装置还包括要启用或禁用的处理逻辑。

9. 发明申请

US20050138335A1 Methods and apparatus to control power consumption within a processor 有权
标题翻译：控制处理器内功耗的方法和装置
公开(公告)号：US20050138335A1
公开(公告)日：2005-06-23
申请号：US10744719
申请日：2003-12-23
申请人： Nicholas Samra , Andrew Huang , Namratha Jaisimha
发明人： Nicholas Samra , Andrew Huang , Namratha Jaisimha
IPC分类号： G06F1/32 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3885 , G06F9/3891 , Y02D10/128 , Y02D10/171
摘要： Methods and apparatus are disclosed to control power consumption within a processor. An example processor disclosed herein comprises an instruction retirement unit; a first set of functional blocks to process a first set of instructions having a first instruction type; a second set of functional blocks to process a second set of instructions having a second instruction type; and a controller to enable the first set of functional blocks to process an instruction allocated to the instruction retirement unit if the type of the instruction is the first type, and to disable the first set of functional blocks after the instruction is retired by the instruction retirement unit.
摘要翻译：公开了用于控制处理器内的功率消耗的方法和装置。本文公开的示例处理器包括指令退出单元; 第一组功能块，用于处理具有第一指令类型的第一组指令; 第二组功能块，用于处理具有第二指令类型的第二组指令; 以及控制器，用于如果所述指令的类型是第一类型，则使得所述第一组功能块能够处理分配给所述指令退出单元的指令，并且在所述指令退出所述指令退出之后禁用所述第一组功能块单元。

10. 发明申请

US20050127490A1 Multi-die processor 审中-公开
标题翻译：多芯片处理器
公开(公告)号：US20050127490A1
公开(公告)日：2005-06-16
申请号：US10738680
申请日：2003-12-16
申请人： Bryan Black , Nicholas Samra , M. Webb
发明人： Bryan Black , Nicholas Samra , M. Webb
IPC分类号： G06F15/78 , G06F17/50 , H01L21/48 , H01L23/48
CPC分类号： G06F15/7832 , H01L24/16 , H01L25/0657 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16145 , H01L2224/73253 , H01L2225/06513 , H01L2225/06562 , H01L2225/06565 , H01L2924/00013 , H01L2924/14 , Y02D10/12 , Y02D10/13 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2924/00 , H01L2924/00014
摘要： Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.
摘要翻译：公开了一种多芯片处理器装置和系统。执行一个或多个指令的处理器逻辑在两个或多个面对面堆叠的骰子之间分配。处理器包括在堆叠的骰子之间的导电接口，以便于管芯到管芯的通信。

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