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1. 发明授权

US06581155B1 Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same 有权
标题翻译：具有无序执行能力的流水线，超标量浮点单元和采用该程序的处理器
公开(公告)号：US06581155B1
公开(公告)日：2003-06-17
申请号：US09382898
申请日：1999-08-25
申请人： Jeffrey Lohman , Nicholas Samra , Ram Gummadi
发明人： Jeffrey Lohman , Nicholas Samra , Ram Gummadi
IPC分类号： G06F9302
CPC分类号： G06F9/3822 , G06F9/3001 , G06F9/3012 , G06F9/3013 , G06F9/30134 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3875
摘要： For use in a processor having a first number of decode units for decoding an ordered stream of floating point instructions, a floating point unit (FPU) for receiving decoded ones of the floating point instructions and a method of processing the decoded ones of the floating point instructions. In one embodiment, the FPU includes: (1) a second number of floating point pipelines that execute the floating point instructions, the second number being at least one and less than the first number, the floating point pipeline having a load unit, an execution core and a store unit, (2) a floating point checkpoint buffer, coupled to the decode units, that queues the decoded ones of the floating point instructions for allocation to the floating point pipelines and (3) a floating point register file, coupled to and cooperable with the floating point checkpoint buffer, that preserves states of the execution core to allow the floating point pipelines to execute the floating point instructions out of order.
摘要翻译：为了在具有用于解码浮点指令的有序流的第一数量的解码单元的处理器中使用用于接收浮点指令的解码的浮点指令的浮点单元（FPU），以及处理浮点的解码单元说明。在一个实施例中，FPU包括：（1）执行浮点指令的第二数量的浮点流水线，第二数量至少为第一数量，并且小于第一数量，浮点流水线具有负载单元，执行核心和存储单元，（2）耦合到解码单元的浮点检查点缓冲器，对解码的浮点指令进行排队以分配给浮点流水线;以及（3）浮点寄存器堆，耦合到并与浮点检查点缓冲区配合，保留执行核心的状态，以允许浮点管道按顺序执行浮点指令。

2. 发明授权

US06907518B1 Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same 有权
标题翻译：具有无序执行能力的流水线，超标量浮点单元和采用该程序的处理器
公开(公告)号：US06907518B1
公开(公告)日：2005-06-14
申请号：US10462585
申请日：2003-06-16
申请人： Jeffrey Lohman , Nicholas Samra , Ram Gummadi
发明人： Jeffrey Lohman , Nicholas Samra , Ram Gummadi
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/3001 , G06F9/3012 , G06F9/3013 , G06F9/30134 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3875
摘要： For use in a processor having a first number of decode units for decoding an ordered stream of floating point instructions, a floating point unit (FPU) for receiving decoded ones of the floating point instructions and a method of processing the decoded ones of the floating point instructions. In one embodiment, the FPU includes: (1) a second number of floating point pipelines that execute the floating point instructions, the second number being at least one and less than the first number, the floating point pipeline having a load unit, an execution core and a store unit, (2) a floating point checkpoint buffer, coupled to the decode units, that queues the decoded ones of the floating point instructions for allocation to the floating point pipelines and (3) a floating point register file, coupled to and cooperable with the floating point checkpoint buffer, that preserves states of the execution core to allow the floating point pipelines to execute the floating point instructions out of order.
摘要翻译：为了在具有用于解码浮点指令的有序流的第一数量的解码单元的处理器中使用用于接收浮点指令的解码的浮点指令的浮点单元（FPU），以及处理浮点的解码单元说明。在一个实施例中，FPU包括：（1）执行浮点指令的第二数量的浮点流水线，第二数量至少为第一数量，并且小于第一数量，浮点流水线具有负载单元，执行核心和存储单元，（2）耦合到解码单元的浮点检查点缓冲器，对解码的浮点指令进行排队以分配给浮点流水线;以及（3）浮点寄存器堆，耦合到并与浮点检查点缓冲区配合，保留执行核心的状态，以允许浮点管道按顺序执行浮点指令。

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