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1. 发明授权

US09577523B2 Dual mode voltage regulator with reconfiguration capability 有权
标题翻译：具有重新配置能力的双模式稳压器
公开(公告)号：US09577523B2
公开(公告)日：2017-02-21
申请号：US13997306
申请日：2012-03-01
申请人： Nicholas P. Cowley , Andrew D. Talbot , Mark Mudd , Stephen J. Spinks , Keith Pinson , Colin L. Perry , Alan J. Martin , Chi Man Kan , Matthew T. Aitken , William L. Barber , Isaac Ali
发明人： Nicholas P. Cowley , Andrew D. Talbot , Mark Mudd , Stephen J. Spinks , Keith Pinson , Colin L. Perry , Alan J. Martin , Chi Man Kan , Matthew T. Aitken , William L. Barber , Isaac Ali
IPC分类号： H02M3/158 , H02M3/156 , H02M3/157 , H02M1/00
CPC分类号： H02M3/158 , H02M2001/0032 , H02M2001/0045 , Y02B70/16
摘要： A dual mode voltage regulator according to one embodiment includes a passive regulator circuit, a switching regulator circuit, and a controller circuit configured to determine parameters of an external select input. The controller is configured to selectively couple, on a cold boot up, either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load based on the determination of parameters.
摘要翻译：根据一个实施例的双模式电压调节器包括无源调节器电路，开关调节器电路和被配置为确定外部选择输入的参数的控制器电路。控制器被配置为基于参数的确定，在冷启动时选择性地将无源调节器电路或开关调节器电路耦合在输入电压端口和输出负载之间。

2. 发明申请

US20150042295A1 DUAL MODE VOLTAGE REGULATOR WITH RECONFIGURATION CAPABILITY 有权
标题翻译：具有重新配置能力的双模电压稳压器
公开(公告)号：US20150042295A1
公开(公告)日：2015-02-12
申请号：US13997306
申请日：2012-03-01
申请人： Nicholas P. Cowley , Andrew D. Talbot , Mark Mudd , Stephen J. Spinks , Keith Pinson , Colin L. Perry , ALAN J. Martin , Chi Man Kan , Matthew T. Aitken , William L. Barber , Isaac Ali
发明人： Nicholas P. Cowley , Andrew D. Talbot , Mark Mudd , Stephen J. Spinks , Keith Pinson , Colin L. Perry , ALAN J. Martin , Chi Man Kan , Matthew T. Aitken , William L. Barber , Isaac Ali
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , H02M2001/0032 , H02M2001/0045 , Y02B70/16
摘要： A dual mode voltage regulator according to one embodiment includes a passive regulator circuit, a switching regulator circuit, and a controller circuit configured to determine parameters of an external select input. The controller is configured to selectively couple, on a cold boot up, either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load based on the determination of parameters.
摘要翻译：根据一个实施例的双模式电压调节器包括无源调节器电路，开关调节器电路和被配置为确定外部选择输入的参数的控制器电路。控制器被配置为基于参数的确定，在冷启动时选择性地将无源调节器电路或开关调节器电路耦合在输入电压端口和输出负载之间。

3. 发明授权

US09343963B2 Dual mode voltage regulator with dynamic reconfiguration capability 有权
标题翻译：具有动态重新配置功能的双模式稳压器
公开(公告)号：US09343963B2
公开(公告)日：2016-05-17
申请号：US13994810
申请日：2011-12-22
申请人： Nicholas P. Cowley , Andrew D. Talbot , Isaac Ali , Keith Pinson , Colin L. Perry , Matthew T. Aitken , Chi Man Kan , Mark S. Mudd , Stephen J. Spinks , Alan J. Martin , William L. Barber
发明人： Nicholas P. Cowley , Andrew D. Talbot , Isaac Ali , Keith Pinson , Colin L. Perry , Matthew T. Aitken , Chi Man Kan , Mark S. Mudd , Stephen J. Spinks , Alan J. Martin , William L. Barber
IPC分类号： H02M3/156 , G05F1/46 , H02M3/158 , H02M1/00
CPC分类号： H02M3/156 , G05F1/46 , H02M3/158 , H02M2001/0045
摘要： A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal.
摘要翻译：根据一个实施例的双模式电压调节器包括无源调节器电路; 开关稳压电路; 以及控制器电路，被配置为监视双模式电压调节器的操作参数，并且在输入电压端口和输出负载之间选择性地耦合无源调节器电路或开关调节器电路。选择耦合是基于对参数的监视，包括输出负载的电流，输入电压端口的电压和输出负载的电压以及系统时钟信号的可用性。

4. 发明申请

US20150035507A1 DUAL MODE VOLTAGE REGULATOR WITH DYNAMIC RECONFIGURATION CAPABILITY 有权
标题翻译：具有动态重构能力的双模电压调节器
公开(公告)号：US20150035507A1
公开(公告)日：2015-02-05
申请号：US13994810
申请日：2011-12-22
申请人： Nicholas P. Cowley , Andrew D. Talbot , Isaac Ali , Keith Pinson , Colin L. Perry , Matthew T. Aitken , Chi Man Kan , Mark S. Mudd , Stephen J. Spinks , Alan J. Martin , William L. Barber
发明人： Nicholas P. Cowley , Andrew D. Talbot , Isaac Ali , Keith Pinson , Colin L. Perry , Matthew T. Aitken , Chi Man Kan , Mark S. Mudd , Stephen J. Spinks , Alan J. Martin , William L. Barber
IPC分类号： H02M3/156
CPC分类号： H02M3/156 , G05F1/46 , H02M3/158 , H02M2001/0045
摘要： A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal.
摘要翻译：根据一个实施例的双模式电压调节器包括无源调节器电路; 开关稳压电路; 以及控制器电路，被配置为监视双模式电压调节器的操作参数，并且在输入电压端口和输出负载之间选择性地耦合无源调节器电路或开关调节器电路。选择耦合是基于对参数的监视，包括输出负载的电流，输入电压端口的电压和输出负载的电压以及系统时钟信号的可用性。

5. 发明申请

US20120249107A1 COUPLED INDUCTOR TO FACILITATE INTEGRATED POWER DELIVERY 审中-公开
标题翻译：耦合电感器，以便于整合电力输送
公开(公告)号：US20120249107A1
公开(公告)日：2012-10-04
申请号：US13078333
申请日：2011-04-01
申请人： Nicholas P. Cowley , Isaac Ali , Stephen J. Spinks
发明人： Nicholas P. Cowley , Isaac Ali , Stephen J. Spinks
IPC分类号： G05F1/00 , H01F41/06 , H01F5/02
CPC分类号： H02M3/1584 , H01F17/02 , Y10T29/49071
摘要： An embodiment of the present invention provides an apparatus, comprising a surface mounted device (SMD) inductor, the SMD inductor including at least two counter wound aircoils formed on a same SMD former; wherein the at least two counter wound aircoils are connected to three terminals on the SMD former, wherein a single terminal is connected to a common node of both windings with two independent terminals accessing the other winding node.
摘要翻译：本发明的一个实施例提供了一种包括表面安装器件（SMD）电感器的装置，所述SMD电感器包括形成在同一SMD形成器上的至少两个反绕绕的电极; 其中所述至少两个计数器缠绕的空心体连接到所述SMD形成器上的三个端子，其中单个端子连接到两个绕组的公共节点，其中两个独立的端子接近另一绕组节点。

6. 发明授权

US08866650B2 Apparatus, systems and methods for for digital testing of ADC/DAC combination 有权
标题翻译：用于ADC / DAC组合的数字测试的装置，系统和方法
公开(公告)号：US08866650B2
公开(公告)日：2014-10-21
申请号：US13992765
申请日：2011-12-07
申请人： Stephen J. Spinks , Andrew Talbot , Colin Mair
发明人： Stephen J. Spinks , Andrew Talbot , Colin Mair
IPC分类号： H03M1/10 , H03M1/46 , H03M1/66
CPC分类号： H03M1/1071 , H03M1/10 , H03M1/109 , H03M1/365 , H03M1/46 , H03M1/66 , H03M1/765
摘要： A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches.
摘要翻译：提供了一个用于测试数模（DAC）和模数转换器（ADC）的电路。电路将具有多个顺序值的码模式应用于数模转换器。多个内置测试开关（BTS）将来自DAC的至少一个抽头电压耦合到测试总线，并将ADC作为可变参考输入电压耦合。在一种形式中，电路使用增量数字代码来测试构成DAC一部分的电阻串，开关阵列和解码逻辑中的缺陷。在另一种形式中，电路使用DAC的抽头电压来测试形成ADC一部分的比较器。代替执行耗时的模数转换，通过改变参考点周围的码模式，并通过选择BTS交换机的适当组合来测试上述电路的功能。

7. 发明申请

US20140191890A1 APPARATUS, SYSTEMS AND METHODS FOR FOR DIGITAL TESTING OF ADC/DAC COMBINATION 有权
标题翻译：用于ADC / DAC组合数字测试的装置，系统和方法
公开(公告)号：US20140191890A1
公开(公告)日：2014-07-10
申请号：US13992765
申请日：2011-12-07
申请人： Stephen J. Spinks , Andrew Talbot , Colin Mair
发明人： Stephen J. Spinks , Andrew Talbot , Colin Mair
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/10 , H03M1/109 , H03M1/365 , H03M1/46 , H03M1/66 , H03M1/765
摘要： A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches.
摘要翻译：提供了一个用于测试数模（DAC）和模数转换器（ADC）的电路。电路将具有多个顺序值的码模式应用于数模转换器。多个内置测试开关（BTS）将来自DAC的至少一个抽头电压耦合到测试总线，并将ADC作为可变参考输入电压耦合。在一种形式中，电路使用增量数字代码来测试构成DAC一部分的电阻串，开关阵列和解码逻辑中的缺陷。在另一种形式中，电路使用DAC的抽头电压来测试形成ADC一部分的比较器。代替执行耗时的模数转换，通过改变参考点周围的码模式，并通过选择BTS交换机的适当组合来测试上述电路的功能。

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