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1. 发明授权

US5167511A High density interconnect apparatus 失效
标题翻译：高密度互连设备
公开(公告)号：US5167511A
公开(公告)日：1992-12-01
申请号：US618603
申请日：1990-11-27
申请人： Nicholas J. Krajewski , Carl D. Breske , David J. Johnson , David R. Kiefer , Kent T. McDaniel , William T. Moore, Jr. , Michael R. Edwards , Bricky A. Stephenson , Anthony A. Vacca
发明人： Nicholas J. Krajewski , Carl D. Breske , David J. Johnson , David R. Kiefer , Kent T. McDaniel , William T. Moore, Jr. , Michael R. Edwards , Bricky A. Stephenson , Anthony A. Vacca
IPC分类号： H01R4/01 , H01R12/50 , H01R12/62 , H01R12/71 , H01R12/82 , H05K1/14 , H05K3/32 , H05K3/40 , H05K7/14
CPC分类号： H01R12/62 , H01R12/71 , H01R12/82 , H01R23/68 , H01R4/01 , H05K7/1444 , H05K1/14 , H05K1/145 , H05K3/325 , H05K3/403
摘要： The invention comprises a plurality of stacked planar processing circuit boards surrounded on at least one side by a plurality of memory boards located substantially perpendicular to the planar processing boards, the processing and memory boards connected by orthogonal interconnect modules. The orthogonal interconnect modules allow closely-spaced orthogonal connection of the processing boards to the memory boards. The memory boards are of a densely packed design having a plurality of removeable memory chip stacks located on the memory boards.
摘要翻译：本发明包括多个层叠的平面处理电路板，其由至少一侧由基本上垂直于平面处理板定位的多个存储器板，由正交互连模块连接的处理器和存储器板包围。正交互连模块允许处理板与存储板的紧密间隔的正交连接。存储器板具有密集封装的设计，其具有位于存储器板上的多个可移除的存储芯片堆叠。

2. 发明授权

US5211565A High density interconnect apparatus 失效
标题翻译：高密度互连设备
公开(公告)号：US5211565A
公开(公告)日：1993-05-18
申请号：US854312
申请日：1992-03-19
申请人： Nicholas J. Krajewski , Carl D. Breske , David J. Johnson , David R. Kiefer , Kent T. McDaniel , William T. Moore, Jr. , Michael R. Edwards , Bricky A. Stephenson , Anthony A. Vacca
发明人： Nicholas J. Krajewski , Carl D. Breske , David J. Johnson , David R. Kiefer , Kent T. McDaniel , William T. Moore, Jr. , Michael R. Edwards , Bricky A. Stephenson , Anthony A. Vacca
IPC分类号： H01R4/01 , H01R12/50 , H01R12/71 , H01R12/79 , H01R12/82 , H05K1/14 , H05K3/32 , H05K3/40 , H05K7/14
CPC分类号： H01R12/71 , H01R12/79 , H01R12/82 , H01R23/68 , H01R4/01 , H05K7/1444 , H05K1/14 , H05K1/145 , H05K3/325 , H05K3/403
摘要： The invention comprises a plurality of stacked planar processing circuit boards surrounded on at least one side by a plurality of memory boards located substantially perpendicular to the planar processing boards, the processing and memory boards connected by orthogonal interconnect modules. The orthogonal interconnect modules allow closely-spaced orthogonal connection of the processing boards to the memory boards. The memory boards are of a densely packed design having a plurality of removeable memory chip stacks located on the memory boards.
摘要翻译：本发明包括多个层叠的平面处理电路板，其由至少一侧由基本上垂直于平面处理板定位的多个存储器板，由正交互连模块连接的处理器和存储器板包围。正交互连模块允许处理板与存储板的紧密间隔的正交连接。存储器板具有密集封装的设计，其具有位于存储器板上的多个可移除的存储芯片堆叠。

3. 发明授权

US5623698A Memory interconnect network having separate routing networks for inputs and outputs using switches with FIFO queues and message steering bits 失效
标题翻译：存储器互连网络具有用于具有FIFO队列和消息导向位的交换机的用于输入和输出的分离的路由网络
公开(公告)号：US5623698A
公开(公告)日：1997-04-22
申请号：US55814
申请日：1993-04-30
申请人： Bricky A. Stephenson , Peter G. Logghe
发明人： Bricky A. Stephenson , Peter G. Logghe
IPC分类号： G06F15/167 , G06F15/173 , G06F13/00
CPC分类号： G06F15/17393
摘要： A processor to memory interconnect network can be used to construct both small and large scale multiprocessing systems. The interconnect network includes network modules and memory modules. The network and memory modules are constructed of a series of n.times.m switches, each of which route n inputs to m outputs. The switches are designed such that message contention in the interconnect network is reduced. The switches, and thus the memory and network modules are highly modular, thus allowing virtually any scale multiprocessing system to be constructed utilizing the same components.
摘要翻译：处理器到存储器互连网络可用于构建小型和大型多处理系统。互连网络包括网络模块和存储器模块。网络和存储器模块由一系列nxm开关构成，每个开关将n个输入端路由到m个输出。交换机被设计成使得互连网络中的消息争用减少。因此，交换机，因此存储器和网络模块是高度模块化的，因此允许使用相同组件来构建几乎任何规模的多处理系统。

4. 发明授权

US5392292A Configurable spare memory chips 失效
标题翻译：可配置的备用内存芯片
公开(公告)号：US5392292A
公开(公告)日：1995-02-21
申请号：US149967
申请日：1993-11-10
申请人： Thomas J. Davis , Michael T. Bye , Richard D. Pribnow , Bricky A. Stephenson
发明人： Thomas J. Davis , Michael T. Bye , Richard D. Pribnow , Bricky A. Stephenson
IPC分类号： G11C29/00 , G06F11/20
CPC分类号： G11C29/848 , G11C29/832
摘要： A memory reconfiguration system dynamically configures spare chips into memory during system operation by shifting data around defective chips. The shifting of data around an entire memory chip allows the system to correct bit, addressing, and control errors or faults within the chip. When the system detects an error, or otherwise initiates a memory reconfiguration, it transmits a configuration code to shift registers for a memory write driver. The shift registers, in response to the configuration code, shift write data so that the data is effectively shifted around a particular memory chip and into a spare memory chip. The system selectively transmits the configuration code to shift registers for a memory read driver. Therefore, the system independently shifts data written to the memory inputs and data read from the memory outputs.
摘要翻译：存储器重新配置系统通过在缺陷芯片周围移动数据来在系统操作期间将备用芯片动态地配置到存储器中。数据在整个存储器芯片周围的移位允许系统校正位，寻址和控制芯片内的错误或故障。当系统检测到错误或以其他方式启动存储器重新配置时，它将配置代码发送到存储器写入驱动器的移位寄存器。移位寄存器响应于配置代码移位写入数据，使得数据被有效地围绕特定存储器芯片移位到备用存储器芯片中。系统选择性地将配置代码发送到用于存储器读取驱动器的移位寄存器。因此，系统独立地将写入存储器输入的数据和从存储器输出读取的数据进行移位。

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