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1. 发明授权

US07979588B1 Data storage system having acceleration path for congested packet switching network 有权
标题翻译：数据存储系统具有拥塞分组交换网络的加速路径
公开(公告)号：US07979588B1
公开(公告)日：2011-07-12
申请号：US11769740
申请日：2007-06-28
申请人： Nhut Tran , Michael Sgrosso , James M. Guyer , William F. Baxter, III
发明人： Nhut Tran , Michael Sgrosso , James M. Guyer , William F. Baxter, III
IPC分类号： G06F15/16 , G06F13/42
CPC分类号： G06F13/387 , G06F2213/0026
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller passes a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译：一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的快速IO格式之间转换分组。控制器包括用于传送原子操作（DSA）请求的PCIE终点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。加速路径控制器在没有网络拥塞的情况下通过DSA缓冲区。馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。

2. 发明授权

US07979572B1 Data storage system having operation code in address portion for atomic operations 有权
标题翻译：具有用于原子操作的地址部分中的操作码的数据存储系统
公开(公告)号：US07979572B1
公开(公告)日：2011-07-12
申请号：US11769737
申请日：2007-06-28
申请人： Nhut Tran , Michael Sgrosso , William F. Baxter, III , James M. Guyer
发明人： Nhut Tran , Michael Sgrosso , William F. Baxter, III , James M. Guyer
IPC分类号： G06F15/16
CPC分类号： G06F13/387 , G06F2213/0026
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译：一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。

3. 发明授权

US07769928B1 Data storage system having CPUs adapted to perform a second atomic operation request prior to completion of a first atomic operation request 有权
标题翻译：具有适于在完成第一原子操作请求之前执行第二原子操作请求的CPU的数据存储系统
公开(公告)号：US07769928B1
公开(公告)日：2010-08-03
申请号：US11769743
申请日：2007-06-28
申请人： Nhut Tran , Michael Sgrosso , William F. Baxter, III , James M. Guyer
发明人： Nhut Tran , Michael Sgrosso , William F. Baxter, III , James M. Guyer
IPC分类号： G06F3/00 , G06F5/00 , G06F13/12 , G06F13/38
CPC分类号： G06F13/387 , G06F2213/0026
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译：一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。控制器包括用于传送原子操作（DSA）请求的PCIE终点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。

4. 发明授权

US07707367B1 Data storage system having separate atomic operation/non-atomic operation paths 有权
标题翻译：数据存储系统具有单独的原子操作/非原子操作路径
公开(公告)号：US07707367B1
公开(公告)日：2010-04-27
申请号：US11769739
申请日：2007-06-28
申请人： Nhut Tran , Michael Sgrosso , William F. Baxter, III , Christopher S. MacLellan
发明人： Nhut Tran , Michael Sgrosso , William F. Baxter, III , Christopher S. MacLellan
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/16 , G06F3/00 , G06F5/00
CPC分类号： G06F13/4054
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译：一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。

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