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1. 发明授权

US06255671B1 Metal embedded passivation layer structure for microelectronic interconnect formation, customization and repair 失效
标题翻译：金属嵌入式钝化层结构，用于微电子互连形成，定制和修复
公开(公告)号：US06255671B1
公开(公告)日：2001-07-03
申请号：US09002840
申请日：1998-01-05
申请人： Nestor Alexander Bojarczuk, Jr. , Supratik Guha , Arunava Gupta , Sampath Purushothaman
发明人： Nestor Alexander Bojarczuk, Jr. , Supratik Guha , Arunava Gupta , Sampath Purushothaman
IPC分类号： H01L3300
CPC分类号： H01L21/76894 , H01L21/76823 , H01L21/76838 , H01L23/5254 , H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure includes a metal nitride film of the form MN, where M is selected from the group consisting of Ga, In, AlGa, AlIn, and AlGaIn. The structure has at least one electrically conductive metal region that is formed within and from the metal nitride film by a thermal process driven by absorption of light having a predetermined wavelength. Single films comprised of AlN are also within the scope of this invention, wherein an Al trace or interconnect is formed by laser radiation of wavelength 248 nm so as to contact circuitry that exists under the film. Multilayered stacks of films are also within the scope of the teachings of this invention. In this case each film layer may be separately deposited and then illuminated to selectively form the desired electrical connection(s), which may also connect to conductive feature(s) in an underlying layer, or a plurality of metal nitride layers are stacked bottom to top in order of increasing electronic band gap energy value, and then the conductive features are written into selective ones of the layers by controlling the wavelength of the light to be absorbed in a desired layer. The teachings of this invention can be employed to fabricate fuses and anti-fuses enabling selective circuit customization, test and repair. Also disclosed is a technique for forming electrical resistors in a metal nitride layer by adjusting the electrical resistance of the metallization formed from the metal nitride film layer.
摘要翻译：结构包括形式为MN的金属氮化物膜，其中M选自Ga，In，AlGa，AlIn和AlGaIn。该结构具有通过由具有预定波长的光吸收驱动的热处理而形成在金属氮化物膜内和从金属氮化物膜形成的至少一个导电金属区域。由AlN组成的单个膜也在本发明的范围内，其中通过波长为248nm的激光辐射形成Al迹线或互连，以便接触存在于膜下面的电路。多层薄膜也在本发明的教导的范围内。在这种情况下，每个膜层可以被分开沉积，然后照亮以选择性地形成所需的电连接，其也可以连接到下层中的导电特征，或者多个金属氮化物层被堆叠到底部顶部按照增加电子带隙能量值的顺序，然后通过控制要在所需层中吸收的光的波长将导电特征写入选择层中。本发明的教导可用于制造保险丝和抗熔丝，从而能够进行选择性电路定制，测试和修理。还公开了通过调整由金属氮化物膜层形成的金属化层的电阻来形成金属氮化物层中的电阻器的技术。

2. 发明申请

US20180340100A1 ENHANCED ADHESIVE MATERIALS AND PROCESSES FOR 3D APPLICATIONS 审中-公开
公开(公告)号：US20180340100A1
公开(公告)日：2018-11-29
申请号：US16004028
申请日：2018-06-08
申请人： James L. Hedrick , Robert Dennis Miller , Deborah Ann Neumayer , Sampath Purushothaman , Mary E. Rothwell , Willi Volksen , Roy R. Yu , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： James L. Hedrick , Robert Dennis Miller , Deborah Ann Neumayer , Sampath Purushothaman , Mary E. Rothwell , Willi Volksen , Roy R. Yu
IPC分类号： C09J9/00 , H01L25/00 , C09J11/04 , H01L23/00 , H01L23/48 , H01L21/768 , H01L21/683 , C09J183/04 , C09J179/08 , C09J179/04 , C09J11/06 , H01L25/065 , C08K7/24 , C08K5/548 , C08K5/5465 , C08K5/544 , C08K5/5425 , B82Y40/00 , B82Y30/00 , C08K3/04
摘要： The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

3. 发明申请

US20170271207A9 Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby 审中-公开
公开(公告)号：US20170271207A9
公开(公告)日：2017-09-21
申请号：US13972396
申请日：2013-08-21
申请人： Sampath Purushothaman , Roy R. Yu
发明人： Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L21/768 , H01L21/762 , H01L23/538
CPC分类号： H01L21/76897 , H01L21/76256 , H01L21/76898 , H01L23/5384 , H01L23/5389 , H01L25/0657 , H01L2224/11 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

4. 发明授权

US08901741B2 Interconnect structures with engineered dielectrics with nanocolumnar porosity 有权
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US08901741B2
公开(公告)日：2014-12-02
申请号：US13531518
申请日：2012-06-23
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

5. 发明授权

US08778736B2 Capping coating for 3D integration applications 失效
公开(公告)号：US08778736B2
公开(公告)日：2014-07-15
申请号：US12192367
申请日：2008-08-15
申请人： Sampath Purushothaman , Anna W. Topol
发明人： Sampath Purushothaman , Anna W. Topol
IPC分类号： H01L21/00
CPC分类号： H01L21/0217 , H01L21/02126 , H01L21/02266 , H01L21/56 , H01L21/6835 , H01L23/3164 , H01L25/50 , H01L2221/68359 , H01L2224/45147 , H01L2225/06513 , H01L2924/00014 , H01L2924/01015 , H01L2924/00 , H01L2224/48
摘要： A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

6. 发明申请

US20140024146A1 SEMICONDUCTOR STRUCTURE 审中-公开
公开(公告)号：US20140024146A1
公开(公告)日：2014-01-23
申请号：US13565848
申请日：2012-08-03
申请人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
发明人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
IPC分类号： H01L21/768 , H01L21/50 , H01L21/66
CPC分类号： H01L23/585 , H01L23/562 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2225/06551 , H01L2225/06565
摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

7. 发明申请

US20130307139A1 BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC AND STRUCTURES SO FORMED 有权
标题翻译：包括金属介电模式在内的金属与电介质结构的结合，形成结构
公开(公告)号：US20130307139A1
公开(公告)日：2013-11-21
申请号：US13443418
申请日：2012-04-10
申请人： Kuan-Neng Chen , Bruce K. Furman , Sampath Purushothaman , David L. Rath , Anna W. Topol , Cornelia K. Tsang
发明人： Kuan-Neng Chen , Bruce K. Furman , Sampath Purushothaman , David L. Rath , Anna W. Topol , Cornelia K. Tsang
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , B23K20/023 , B23K20/233 , B23K20/24 , B23K2101/42 , H01L24/03 , H01L24/08 , H01L24/12 , H01L24/80 , H01L2224/0381 , H01L2224/03845 , H01L2224/0401 , H01L2224/05571 , H01L2224/05572 , H01L2224/08147 , H01L2224/08148 , H01L2224/80203 , H01L2224/80345 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/80986 , H01L2924/14 , H01L2924/1461 , Y10T428/24479 , Y10T428/24521 , Y10T428/24545 , Y10T428/24612 , Y10T428/31678 , H01L2924/00012 , H01L2924/0001 , H01L2924/00
摘要： Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.
摘要翻译：公开了包括金属电介质图案在表面上与在电介质上方凸起的金属以及相关结构的接合。一种方法包括在其表面上提供具有金属 - 电介质图案的第一基板; 提供在其表面上具有金属 - 电介质图案的第二基板; 执行导致金属在电介质上方升高的过程; 清洗金属; 以及将所述第一基板接合到所述第二基板。还公开了相关的结构。凸起金属的结合提供了强大的粘合介质，以及良好的电气和热连接，能够创建具有增强功能的三维集成结构。

8. 发明授权

US08492869B2 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer 有权
标题翻译：具有在较高成本的有源电路层之前堆叠的低成本有源电路层的3D集成电路器件
公开(公告)号：US08492869B2
公开(公告)日：2013-07-23
申请号：US13571920
申请日：2012-08-10
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/50
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L21/8221 , H01L25/0657 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L2221/68377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0557 , H01L2224/131 , H01L2224/16 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/80001 , H01L2924/014 , H01L2224/83 , H01L2224/11
摘要： A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.
摘要翻译：提供了3D集成电路结构。 3D集成电路结构包括接口晶片，其包括第一布线层，包括有源电路的第一有源电路层和包括有源电路的晶片。第一有源电路层面向下接合到接口晶片，并且晶片正面朝下地接合到第一有源电路层。第一有源电路层比晶片成本低。

9. 发明授权

US08415248B2 Self-aligned dual damascene BEOL structures with patternable low-k material and methods of forming same 有权
标题翻译：具有可编程低k材料的自对准双镶嵌BEOL结构及其形成方法
公开(公告)号：US08415248B2
公开(公告)日：2013-04-09
申请号：US13474349
申请日：2012-05-17
申请人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
发明人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/4846 , H01L21/76801 , H01L21/76808 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/49894 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.
摘要翻译：提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案）其中。具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。导电材料填充至少一个第一互连图案和至少一个第二互连图案。还提供了形成这种自对准互连结构的方法。

10. 发明授权

US08399336B2 Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer 有权
标题翻译：用于制造具有在较高成本的有源电路层之前堆叠的较低成本有源电路层的3D集成电路器件的方法
公开(公告)号：US08399336B2
公开(公告)日：2013-03-19
申请号：US12194211
申请日：2008-08-19
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L21/8221 , H01L25/0657 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L2221/68377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0557 , H01L2224/131 , H01L2224/16 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/80001 , H01L2924/014 , H01L2224/83 , H01L2224/11
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。第一有源电路层晶片比另一个晶片低成本。还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

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