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1. 发明授权

US07169674B2 Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier 有权
标题翻译：具有高介电常数栅极电介质和集成扩散势垒的互补金属氧化物半导体（CMOS）栅极叠层
公开(公告)号：US07169674B2
公开(公告)日：2007-01-30
申请号：US11066762
申请日：2005-02-28
申请人： Nestor Alexander Bojarczuk, Jr. , Kevin Kok Chan , Christopher Peter D'Emic , Evgeni Gousev , Supratik Guha , Paul C. Jamison , Lars-Ake Ragnarsson
发明人： Nestor Alexander Bojarczuk, Jr. , Kevin Kok Chan , Christopher Peter D'Emic , Evgeni Gousev , Supratik Guha , Paul C. Jamison , Lars-Ake Ragnarsson
IPC分类号： H01L21/8236 , H01L21/8222 , H01L21/335 , H01L21/8234 , H01L21/336 , H01L21/331
CPC分类号： H01L29/513 , H01L21/28194
摘要： A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.
摘要翻译：用于具有沟道区和栅电极的场效应晶体管的扩散势垒（和形成扩散势垒的方法）包括设置在沟道区上的绝缘材料。绝缘材料包括氮（N），并且设置在栅电极下方。绝缘材料可以设置为层或分布在设置在栅电极下方的栅极电介质材料内。

2. 发明授权

US06891231B2 Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier 有权
标题翻译：具有高介电常数栅极电介质和集成扩散势垒的互补金属氧化物半导体（CMOS）栅极叠层
公开(公告)号：US06891231B2
公开(公告)日：2005-05-10
申请号：US09879105
申请日：2001-06-13
申请人： Nestor Alexander Bojarczuk, Jr. , Kevin Kok Chan , Christopher Peter D'Emic , Evgeni Gousev , Supratik Guha , Paul C. Jamison , Lars-Ake Ragnarsson
发明人： Nestor Alexander Bojarczuk, Jr. , Kevin Kok Chan , Christopher Peter D'Emic , Evgeni Gousev , Supratik Guha , Paul C. Jamison , Lars-Ake Ragnarsson
IPC分类号： H01L21/8238 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/513 , H01L21/28194
摘要： A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.
摘要翻译：用于具有沟道区和栅电极的场效应晶体管的扩散势垒（和形成扩散势垒的方法）包括设置在沟道区上的绝缘材料。绝缘材料包括氮（N），并且设置在栅电极下方。绝缘材料可以设置为层或分布在设置在栅电极下方的栅极电介质材料内。

3. 发明授权

US06573197B2 Thermally stable poly-Si/high dielectric constant material interfaces 有权
公开(公告)号：US06573197B2
公开(公告)日：2003-06-03
申请号：US09833550
申请日：2001-04-12
申请人： Alessandro C. Callegari , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Dianne L. Lacey
发明人： Alessandro C. Callegari , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Dianne L. Lacey
IPC分类号： H01L2131
CPC分类号： H01L21/02304 , C23C16/24 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/02189 , H01L21/02197 , H01L21/0223 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/28035 , H01L21/28194 , H01L21/28202 , H01L21/28525 , H01L21/28556 , H01L21/31604 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention provides a method of fabricating a thermally stable polysilicon/high-k dielectric film stack utilizing a deposition method wherein Si-containing precursor gas which includes silicon and hydrogen is diluted with an inert gas such as He so as to significantly reduce the hydrogen content in the resultant polysilicon film. Semiconductor structures such as field effect transistors (FETs) and capacitors which include at least the thermally stable polysilicon/high-k dielectric film stack are also provided herein.

4. 发明授权

US08153514B2 Method of forming metal/high-κ gate stacks with high mobility 有权
标题翻译：金属/高分子金属成型方法移动性高的门栈
公开(公告)号：US08153514B2
公开(公告)日：2012-04-10
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, Jr. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, Jr. , Sufi Zafar
IPC分类号： H01L21/3205
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高迁移率和低界面电荷的栅叠层结构，以及包括其的半导体器件即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了一种栅极叠层结构，其具有约8×10 10电荷/ cm 2或更小的峰值迁移率，约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度，以及在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。

5. 发明申请

US20080293259A1 METHOD OF FORMING METAL/HIGH-k GATE STACKS WITH HIGH MOBILITY 有权
标题翻译：形成具有高移动性的金属/高k栅极堆叠的方法
公开(公告)号：US20080293259A1
公开(公告)日：2008-11-27
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
IPC分类号： H01L21/263
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

6. 发明授权

US07242055B2 Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide 失效
标题翻译：包含通过沉积金属氧化物形成的阈值电压控制层的含氮场效应晶体管栅叠层
公开(公告)号：US07242055B2
公开(公告)日：2007-07-10
申请号：US10988733
申请日：2004-11-15
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Paul C. Jamison , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Paul C. Jamison , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/2822 , H01L21/823828 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518
摘要： A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vt stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.
摘要翻译：提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。本发明还提供一种制造这种结构的方法。

7. 发明授权

US09006094B2 Stratified gate dielectric stack for gate dielectric leakage reduction 有权
标题翻译：用于栅介质泄漏减少的分层栅极电介质叠层
公开(公告)号：US09006094B2
公开(公告)日：2015-04-14
申请号：US13449647
申请日：2012-04-18
申请人： Hemanth Jagannathan , Paul C. Jamison
发明人： Hemanth Jagannathan , Paul C. Jamison
IPC分类号： H01L21/20 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L21/28
CPC分类号： H01L21/283 , H01L21/28158 , H01L21/28202 , H01L21/28211 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L29/7833 , H01L29/785
摘要： A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.
摘要翻译：分层栅极电介质堆叠包括第一高介电常数（high-k）栅极电介质，其包括第一高k电介质材料，带隙破坏电介质，其包含具有与第一高k电介质不同带隙的电介质材料材料和包含第二高k电介质材料的第二高k栅极电介质。带隙破坏电介质包括介电材料的至少一个连续的原子层。因此，分层栅极电介质堆叠包括第一高k栅极电介质和带隙破坏电介质之间的第一原子界面，以及第二高k栅极电介质和带隙破坏电介质之间的第二原子界面其与带隙破坏电介质的电介质材料的至少一个连续原子层与第一原子界面间隔开。带隙干扰介质的插入导致较低的栅极泄漏，而不会导致阈值电压特性和有效氧化物厚度的任何实质性变化。

8. 发明申请

US20130280902A1 STRATIFIED GATE DIELECTRIC STACK FOR GATE DIELECTRIC LEAKAGE REDUCTION 有权
公开(公告)号：US20130280902A1
公开(公告)日：2013-10-24
申请号：US13449647
申请日：2012-04-18
申请人： Hemanth Jagannathan , Paul C. Jamison
发明人： Hemanth Jagannathan , Paul C. Jamison
IPC分类号： H01L21/28
CPC分类号： H01L21/283 , H01L21/28158 , H01L21/28202 , H01L21/28211 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L29/7833 , H01L29/785
摘要： A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.

9. 发明授权

US06511876B2 High mobility FETS using A1203 as a gate oxide 有权
标题翻译：使用Al2O3作为栅极氧化物的高迁移率FET
公开(公告)号：US06511876B2
公开(公告)日：2003-01-28
申请号：US09888777
申请日：2001-06-25
申请人： Douglas A. Buchanan , Alessandro C. Callegari , Michael A. Gribelyuk , Paul C. Jamison , Deborah Ann Neumayer
发明人： Douglas A. Buchanan , Alessandro C. Callegari , Michael A. Gribelyuk , Paul C. Jamison , Deborah Ann Neumayer
IPC分类号： H01C218242
CPC分类号： H01L21/28185 , H01L21/02178 , H01L21/02271 , H01L21/02304 , H01L21/28194 , H01L21/28202 , H01L21/31616 , H01L21/3162 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250° C. or above) such that the substrate wafer is not cooled during the various processing steps. Such a method leads to the formation of a high-k dielectric material which does not exhibit a hysteric behavior in a capacitance-voltage curve as well as an increased mobility on FETs using conventional CMOS processing.
摘要翻译：提供了一种形成在栅极堆叠区域内呈现基本较低量的陷阱电荷的高k电介质材料的方法。该方法保持高温（250℃或以上），使得在各种处理步骤期间基板晶片不被冷却。这种方法导致形成高k电介质材料，其在电容 - 电压曲线中不表现出歇斯底里行为，并且使用常规CMOS处理在FET上增加迁移率。

10. 发明授权

US06355567B1 Retrograde openings in thin films 失效
标题翻译：薄膜逆行开口
公开(公告)号：US06355567B1
公开(公告)日：2002-03-12
申请号：US09345646
申请日：1999-06-30
申请人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
发明人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
IPC分类号： H01L21311
CPC分类号： H01L21/76879 , H01L21/31116 , H01L21/76804 , H01L21/7682 , H01L21/76885
摘要： Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.
摘要翻译：薄膜中的逆行开口及其形成方法。开口可以包括形成在开口内的导电材料，以用作包括具有锥形横截面的导线的布线图案。该方法涉及用于在膜内形成具有影响所选择的蚀刻剂物质的蚀刻速率的特性梯度的逆向开口的两步蚀刻方法。首先通过各向异性蚀刻工艺在膜内形成开口。然后通过对特性有选择性的各向同性蚀刻工艺将开口转换成包括逆行特征的开口。此后，逆行开口填充有导电材料，在一种情况下，通过电镀或其它沉积技术。

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