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1. 发明授权

US06299991B1 Selective growth of ferromagnetic films for magnetic memory, storage-based devices 有权
标题翻译：用于磁存储器，存储器件的铁磁膜的选择性增长
公开(公告)号：US06299991B1
公开(公告)日：2001-10-09
申请号：US09172659
申请日：1998-10-15
申请人： Nestor A. Bojarczuk, Jr. , Peter R. Duncombe , Supratik Guha , Arunava Gupta , Joseph M. Karasinski , Xinwei Li
发明人： Nestor A. Bojarczuk, Jr. , Peter R. Duncombe , Supratik Guha , Arunava Gupta , Joseph M. Karasinski , Xinwei Li
IPC分类号： G11B566
CPC分类号： G11B5/7325 , G11B5/855 , Y10T428/24752 , Y10T428/24802
摘要： A device and a method of forming the device, includes selective area deposition of a ferromagnetic material on a substrate. The substrate surface is partially covered with material having a crystal structure having at least one symmetry relation with the crystal structure of the ferromagnetic material
摘要翻译：形成该器件的器件和方法包括将铁磁材料选择性地沉积在衬底上。基板表面部分被具有与铁磁材料的晶体结构至少一个对称关系的晶体结构的材料覆盖

2. 发明授权

US06333067B2 Selective growth of ferromagnetic films 失效
标题翻译：铁磁薄膜的选择性生长
公开(公告)号：US06333067B2
公开(公告)日：2001-12-25
申请号：US09879156
申请日：2001-06-13
申请人： Nestor A. Bojarczuk, Jr. , Peter R. Duncombe , Supratik Guha , Arunava Gupta , Joseph M. Karasinski , Xinwei Li
发明人： Nestor A. Bojarczuk, Jr. , Peter R. Duncombe , Supratik Guha , Arunava Gupta , Joseph M. Karasinski , Xinwei Li
IPC分类号： B05D512
CPC分类号： G11B5/7325 , G11B5/855 , Y10T428/24752 , Y10T428/24802
摘要： A method of forming the device, includes selective area deposition of a ferromagnetic material on a substrate. The substrate surface is partially covered with material having a crystal structure having at least one symmetry relation with the crystal structure of the ferromagnetic material.
摘要翻译：形成该器件的方法包括将铁磁材料选择性地沉积在衬底上。基板表面部分被具有与铁磁材料的晶体结构至少一个对称关系的晶体结构的材料覆盖。

3. 发明授权

US08193051B2 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics 有权
标题翻译：在具有高k电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制
公开(公告)号：US08193051B2
公开(公告)日：2012-06-05
申请号：US13047172
申请日：2011-03-14
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
摘要翻译：本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

4. 发明授权

US07488640B2 Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same 失效
公开(公告)号：US07488640B2
公开(公告)日：2009-02-10
申请号：US10976068
申请日：2004-10-29
申请人： Nestor A. Bojarczuk, Jr. , Eduard Cartier , Supratik Guha , Lars-Ake Ragnarsson
发明人： Nestor A. Bojarczuk, Jr. , Eduard Cartier , Supratik Guha , Lars-Ake Ragnarsson
IPC分类号： H01L21/8238
CPC分类号： H01L21/28202 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.

5. 发明申请

US20090152642A1 SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS 有权
标题翻译：在CMOS设备制造中使用高k电路实现栅极电压控制的障碍层的选择性实现
公开(公告)号：US20090152642A1
公开(公告)日：2009-06-18
申请号：US12355368
申请日：2009-01-16
申请人： Nestor A. Bojarczuk, JR. , Cyril Cabral, JR. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, JR. , Cyril Cabral, JR. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L27/092 , H01L21/336 , H01L21/02
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
摘要翻译：本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

6. 发明授权

US07452767B2 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics 有权
标题翻译：在具有高k电介质的CMOS器件制造中实现阈值电压控制的势垒层的选择性实现
公开(公告)号：US07452767B2
公开(公告)日：2008-11-18
申请号：US11500254
申请日：2006-08-07
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.
摘要翻译：一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。绝缘中间层可以是AlN或AlO x N y Y。高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

7. 发明授权

US06831339B2 Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same 有权
标题翻译：氮化铝和氧化铝/氮化铝异质结构栅极电介质堆叠的场效应晶体管及其形成方法
公开(公告)号：US06831339B2
公开(公告)日：2004-12-14
申请号：US09755164
申请日：2001-01-08
申请人： Nestor A. Bojarczuk, Jr. , Eduard Cartier , Supratik Guha , Lars-Ake Ragnarsson
发明人： Nestor A. Bojarczuk, Jr. , Eduard Cartier , Supratik Guha , Lars-Ake Ragnarsson
IPC分类号： H01L29772
CPC分类号： H01L21/28202 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.
摘要翻译：一种结构（例如场效应晶体管）和一种制造该结构的方法包括：具有源极区，漏极区和沟道区的衬底，设置在沟道区上方的绝缘层，绝缘层包括层包括设置在沟道区域上的氮化铝，以及设置在绝缘层上的栅电极。

8. 发明授权

US06541079B1 Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique 失效
标题翻译：通过原子束沉积技术工程化的高介电常数氧化物和氧氮化物异质结构栅极电介质
公开(公告)号：US06541079B1
公开(公告)日：2003-04-01
申请号：US09426656
申请日：1999-10-25
申请人： Nestor A. Bojarczuk, Jr. , Eduard A. Cartier , Supratik Guha
发明人： Nestor A. Bojarczuk, Jr. , Eduard A. Cartier , Supratik Guha
IPC分类号： C23C1408
CPC分类号： C23C14/22 , C23C14/081
摘要： A method of forming a layer of oxide or oxynitride upon a substrate including first placing a substrate having an upper surface and a lower surface in a high vacuum chamber and then exposing the upper surface to a beam of atoms or molecules, or both, of oxygen or nitrogen or a combination of same at a temperature sufficient to form a reacted layer on the upper surface of said substrate wherein said layer has a chemical composition different from the chemical composition of said substrate. The reacted upper layer is then exposed simultaneously in the chamber to atomic or molecular beams of oxygen, nitrogen or both and to a beam of metal atoms or metal molecules selected from the group consisting of Al, Si, Zr, La, Y, Sc, Sr, Ba, Ti, Ta, W, Cr, Zr, Ca, Mg, Be, Pr, Nd and Hf to form a metal oxide, a metal nitride or a metal oxynitride layer in said layer. Another option is to expose the upper surface of the substrate simultaneously in the chamber to atomic or molecular beams of oxygen, nitrogen or both and to a beam of metal atoms or meal molecules selected from the group consisting of Al, Si, Zr, La Y, Sc, Sr, Ba, Ti, Ta, W, Cr, Zr, Ca, Mg, Be, Pr, Nd and Hf to form a metal oxide, a metal nitride or a metal oxynitride layer on said reacted layer.
摘要翻译：一种在衬底上形成氧化物或氮氧化物层的方法，包括首先将具有上表面和下表面的衬底放置在高真空室中，然后将上表面暴露于原子或分子或两者的氧气束或氮或其组合，其温度足以在所述基材的上表面上形成反应层，其中所述层具有不同于所述基材的化学组成的化学组成。然后将反应的上层在室中同时暴露于氧，氮或两者的原子或分子束，并且暴露于选自Al，Si，Zr，La，Y，Sc等金属原子或金属分子束， Sr，Ba，Ti，Ta，W，Cr，Zr，Ca，Mg，Be，Pr，Nd和Hf，以在所述层中形成金属氧化物，金属氮化物或金属氮氧化物层。另一个选择是将基板的上表面同时暴露于氧，氮或两者的原子或分子束，以及选自Al，Si，Zr，La Y的金属原子或粉末分子束，Sc，Sr，Ba，Ti，Ta，W，Cr，Zr，Ca，Mg，Be，Pr，Nd和Hf，以在所述反应层上形成金属氧化物，金属氮化物或金属氮氧化物层。

9. 发明授权

US07928514B2 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics 有权
标题翻译：在具有高k电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制
公开(公告)号：US07928514B2
公开(公告)日：2011-04-19
申请号：US12355368
申请日：2009-01-16
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/76
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
摘要翻译：本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

10. 发明授权

US07105889B2 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics 有权
标题翻译：在具有高k电介质的CMOS器件制造中实现阈值电压控制的势垒层的选择性实现
公开(公告)号：US07105889B2
公开(公告)日：2006-09-12
申请号：US10863830
申请日：2004-06-04
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.
摘要翻译：一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。绝缘中间层可以是AlN或AlO x N y Y。高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

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