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1. 发明申请

US20090282375A1 Circuit And Method Using Distributed Phase Change Elements For Across-Chip Temperature Profiling 有权
标题翻译：用于跨芯片温度分布的分布相变元件的电路和方法
公开(公告)号：US20090282375A1
公开(公告)日：2009-11-12
申请号：US12117784
申请日：2008-05-09
申请人： Nazmul Habib , Mark C.H. Lamorey , Thomas M. Maffitt , Robert McMahon
发明人： Nazmul Habib , Mark C.H. Lamorey , Thomas M. Maffitt , Robert McMahon
IPC分类号： G06F17/50 , G01K3/00
CPC分类号： G01K3/14 , G01K7/006 , G01K7/425
摘要： Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores.
摘要翻译：公开了一种跨芯片温度感测电路及其相关方法，可用于对片内温度梯度进行分析。这些实施例结合了大致均匀分布在半导体芯片上的多个相变元件。这些相变元件被编程为具有基本上相同的无定形电阻。每个相变元件单独表现出的温度相关行为与参考（例如，由离散参考相变元件产生，由另一个相变元件产生或由外部参考产生）相比较，以便描述半导体芯片上的温度梯度。一旦进行了分析，该温度梯度可用于重新设计和/或重新定位功能核心，为功能核心的鉴定和/或调整功能核心的操作规范设定应力限制。

2. 发明授权

US07882455B2 Circuit and method using distributed phase change elements for across-chip temperature profiling 有权
标题翻译：使用分布式相变元件进行跨芯片温度分析的电路和方法
公开(公告)号：US07882455B2
公开(公告)日：2011-02-01
申请号：US12117784
申请日：2008-05-09
申请人： Nazmul Habib , Mark C. H. Lamorey , Thomas M. Maffitt , Robert McMahon
发明人： Nazmul Habib , Mark C. H. Lamorey , Thomas M. Maffitt , Robert McMahon
IPC分类号： G06F17/50
CPC分类号： G01K3/14 , G01K7/006 , G01K7/425
摘要： Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores.
摘要翻译：公开了一种跨芯片温度感测电路及其相关方法，可用于对片内温度梯度进行分析。这些实施例结合了大致均匀分布在半导体芯片上的多个相变元件。这些相变元件被编程为具有基本上相同的无定形电阻。每个相变元件单独表现出的温度相关行为与参考（例如，由离散参考相变元件产生，由另一个相变元件产生或由外部参考产生）相比较，以便描述半导体芯片上的温度梯度。一旦进行了分析，该温度梯度可用于重新设计和/或重新定位功能核心，为功能核心的鉴定和/或调整功能核心的操作规范设定应力限制。

3. 发明申请

US20090086534A1 APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES 失效
标题翻译：用于实施PCRAM设备精密感测的装置和方法
公开(公告)号：US20090086534A1
公开(公告)日：2009-04-02
申请号：US11865134
申请日：2007-10-01
申请人： John K. DeBrosse , Thomas M. Maffitt , Mark C.H. Lamorey
发明人： John K. DeBrosse , Thomas M. Maffitt , Mark C.H. Lamorey
IPC分类号： G11C11/00 , G11C7/00 , G11C7/10
CPC分类号： G11C29/02 , G11C7/062 , G11C7/067 , G11C13/0004 , G11C13/004 , G11C29/026 , G11C29/028 , G11C2013/0054
摘要： A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.
摘要翻译：精密读出放大器装置包括：电流源，被配置为通过参考支路引入可调参考电流; 配置为将参考电流镜像到数据支路的电流镜，所述数据支路选择性地耦合到可编程电阻存储元件; 耦合到所述数据支脚的有源钳位装置，并且被配置为在所述存储元件上钳位固定电压，由此建立其固定的电流吸收能力; 以及差分读出放大器，其具有耦合到所述数据支路的第一输入端和耦合到所述基准支路的第二输入端; 其中每当所述参考电流小于所述存储元件的固定电流吸收能力时，所述差分读出放大器的输出呈现第一逻辑状态，并且每当所述参考电流超过所述固定电流吸收能力时，所述差分读出放大器的输出呈现第二逻辑状态。

4. 发明申请

US20110116312A1 NON VOLATILE CELL AND ARCHITECTURE WITH SINGLE BIT RANDOM ACCESS READ, PROGRAM AND ERASE 有权
标题翻译：非易失性单元和单个单元随机访问阅读，程序和删除的架构
公开(公告)号：US20110116312A1
公开(公告)日：2011-05-19
申请号：US12619771
申请日：2009-11-17
申请人： Chung H. Lam , Mark C.H. Lamorey , Thomas M. Maffitt
发明人： Chung H. Lam , Mark C.H. Lamorey , Thomas M. Maffitt
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10
摘要： One embodiment is a non-volatile memory cell with random access read, program, and erase. The memory cell includes a cell transistor that includes a source region, a drain region, a first insulating spacer, and a second insulating spacer. The memory cell also includes a source-side transistor, a drain-side transistor, a source-side multiplexer, a drain-side multiplexer, a source-side sense amplifier, and a drain-side write driver. A first binary value is stored in a first bit in the memory cell by trapping or releasing a first electric charge in the first insulating spacer. The first bit is read by sensing the resistive change in the cell transistor or by sensing the threshold voltage change in the cell transistor.
摘要翻译：一个实施例是具有随机访问读取，编程和擦除的非易失性存储单元。存储单元包括一个单元晶体管，它包括一个源极区，一个漏极区，一个第一绝缘间隔物和一个第二绝缘隔离物。存储单元还包括源极晶体管，漏极侧晶体管，源极侧多路复用器，漏极侧多路复用器，源极侧读出放大器和漏极侧写入驱动器。通过在第一绝缘间隔物中捕获或释放第一电荷，将第一二进制值存储在存储器单元中的第一位中。通过感测单元晶体管中的电阻变化或通过感测单元晶体管中的阈值电压变化来读取第一位。

5. 发明授权

US08345475B2 Non volatile cell and architecture with single bit random access read, program and erase 有权
标题翻译：非易失性单元和架构，具有单位随机访问读，编程和擦除
公开(公告)号：US08345475B2
公开(公告)日：2013-01-01
申请号：US12619771
申请日：2009-11-17
申请人： Chung H. Lam , Mark C. H. Lamorey , Thomas M. Maffitt
发明人： Chung H. Lam , Mark C. H. Lamorey , Thomas M. Maffitt
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10
摘要： One embodiment is a non-volatile memory cell with random access read, program, and erase. The memory cell includes a cell transistor that includes a source region, a drain region, a first insulating spacer, and a second insulating spacer. The memory cell also includes a source-side transistor, a drain-side transistor, a source-side multiplexer, a drain-side multiplexer, a source-side sense amplifier, and a drain-side write driver. A first binary value is stored in a first bit in the memory cell by trapping or releasing a first electric charge in the first insulating spacer. The first bit is read by sensing the resistive change in the cell transistor or by sensing the threshold voltage change in the cell transistor.
摘要翻译：一个实施例是具有随机访问读取，编程和擦除的非易失性存储单元。存储单元包括一个单元晶体管，它包括一个源极区，一个漏极区，一个第一绝缘间隔物和一个第二绝缘隔离物。存储单元还包括源极晶体管，漏极侧晶体管，源极侧多路复用器，漏极侧多路复用器，源极侧读出放大器和漏极侧写入驱动器。通过在第一绝缘间隔物中捕获或释放第一电荷，将第一二进制值存储在存储器单元中的第一位中。通过感测单元晶体管中的电阻变化或通过感测单元晶体管中的阈值电压变化来读取第一位。

6. 发明授权

US07778065B2 Method and apparatus for implementing concurrent multiple level sensing operation for resistive memory devices 失效
标题翻译：用于实现电阻式存储器件的并发多电平感测操作的方法和装置
公开(公告)号：US07778065B2
公开(公告)日：2010-08-17
申请号：US12039990
申请日：2008-02-29
申请人： Mark C. H. Lamorey , Thomas M. Maffitt
发明人： Mark C. H. Lamorey , Thomas M. Maffitt
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C11/1673 , G11C11/56 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a programmable resistive memory element, the clamping device configured to clamp a fixed voltage, at a first node of the data leg, across the memory element, thereby establishing a fixed current sinking capability thereof; and a plurality of differential amplifiers, each of the differential amplifiers configured to compare a first voltage input, taken at a second node of the data leg, with a second voltage input; wherein the second voltage input for each differential amplifier comprises different reference voltages with respect to one another so as to enable each differential amplifier to detect a different resistance threshold, thereby determining a specific resistance state of the programmable resistive memory element.
摘要翻译：用于感测多级可编程电阻式存储器件的数据状态的装置包括连接到数据支路的有源钳位装置，该有源钳位装置选择性地耦合可编程电阻性存储器元件，钳位装置被配置为在第一节点处钳位固定电压跨越存储元件，从而建立其固定的电流吸收能力; 以及多个差分放大器，所述差分放大器中的每一个被配置为将在所述数据支路的第二节点处获取的第一电压输入与第二电压输入进行比较; 其中每个差分放大器的第二电压输入包括相对于彼此的不同的参考电压，以使得每个差分放大器能够检测不同的电阻阈值，从而确定可编程电阻式存储器元件的特定电阻状态。

7. 发明授权

US07535783B2 Apparatus and method for implementing precise sensing of PCRAM devices 失效
标题翻译：实现PCRAM设备精确检测的装置和方法
公开(公告)号：US07535783B2
公开(公告)日：2009-05-19
申请号：US11865134
申请日：2007-10-01
申请人： John K. DeBrosse , Thomas M. Maffitt , Mark C. H. Lamorey
发明人： John K. DeBrosse , Thomas M. Maffitt , Mark C. H. Lamorey
IPC分类号： G11C7/02
CPC分类号： G11C29/02 , G11C7/062 , G11C7/067 , G11C13/0004 , G11C13/004 , G11C29/026 , G11C29/028 , G11C2013/0054
摘要： A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.
摘要翻译：精密读出放大器装置包括：电流源，被配置为通过参考支路引入可调参考电流; 配置为将参考电流镜像到数据支路的电流镜，所述数据支路选择性地耦合到可编程电阻存储元件; 耦合到所述数据支脚的有源钳位装置，并且被配置为在所述存储元件上钳位固定电压，由此建立其固定的电流吸收能力; 以及差分读出放大器，其具有耦合到所述数据支路的第一输入端和耦合到所述基准支路的第二输入端; 其中每当所述参考电流小于所述存储元件的固定电流吸收能力时，所述差分读出放大器的输出呈现第一逻辑状态，并且每当所述参考电流超过所述固定电流吸收能力时，所述差分读出放大器的输出呈现第二逻辑状态。

8. 发明授权

US08233345B2 Phase change memory cycle timer and method 有权
标题翻译：相变存储周期定时器和方法
公开(公告)号：US08233345B2
公开(公告)日：2012-07-31
申请号：US12877628
申请日：2010-09-08
申请人： John A Gabric , Mark C. Lamorey , Thomas M. Maffitt
发明人： John A Gabric , Mark C. Lamorey , Thomas M. Maffitt
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.
摘要翻译：公开了一种相变存储器（PCM）周期定时器及相关方法。系统包括至少一个参考相变元件（PCE）。该系统还包括对至少一个参考PCE执行写操作并且基本上立即在该连续感测并且在至少一个参考PCE的整个建立时间内返回至少一个参考PCE的电阻值的电路。

9. 发明授权

US07660152B2 Method and apparatus for implementing self-referencing read operation for PCRAM devices 有权
标题翻译：用于实现PCRAM设备的自参考读取操作的方法和装置
公开(公告)号：US07660152B2
公开(公告)日：2010-02-09
申请号：US12112454
申请日：2008-04-30
申请人： Mark C. Lamorey , Thomas M. Maffitt
发明人： Mark C. Lamorey , Thomas M. Maffitt
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C2013/0057
摘要： A method of implementing a self-referencing read operation for a PCRAM array includes applying a stimulus to a bit line associated with a selected phase change element (PCE) to be read; comparing a first voltage on a node of the bit line with a second voltage on a delay node, wherein the second voltage represents a delayed voltage with respect to the first voltage due to a resistance/capacitance time constant associated therewith; and determining whether, during the read operation, the first voltage drops below the value of the second voltage; wherein in the event the first voltage drops below the value of the second voltage during the read operation, the PCE is determined to be programmed to an amorphous state and in the event the first voltage does not drop below the value of the second voltage, the PCE is determined to be programmed to a crystalline state.
摘要翻译：实现PCRAM阵列的自参考读取操作的方法包括将刺激应用于与要读取的所选择的相变元件（PCE）相关联的位线; 将位线的节点上的第一电压与延迟节点上的第二电压进行比较，其中所述第二电压表示由于与其相关联的电阻/电容时间常数而相对于所述第一电压的延迟电压; 以及确定在所述读取操作期间所述第一电压是否低于所述第二电压的值; 其中在所述读取操作期间所述第一电压下降到所述第二电压值以下的情况下，所述PCE被确定为被编程为非晶状态，并且在所述第一电压不低于所述第二电压值的情况下， PCE被确定为被编程为结晶状态。

10. 发明授权

US6014046A Off chip driver (OCD) with variable drive capability for noise control 失效
标题翻译：具有可变驱动能力的离散驱动器（OCD），用于噪声控制
公开(公告)号：US6014046A
公开(公告)日：2000-01-11
申请号：US904411
申请日：1997-07-31
申请人： David E. Douse , Scott C. Lewis , Thomas M. Maffitt
发明人： David E. Douse , Scott C. Lewis , Thomas M. Maffitt
IPC分类号： H03K19/00 , H03K19/094 , H03B1/00 , H03K3/00
CPC分类号： H03K19/09429 , H03K19/0013
摘要： An Off Chip Driver (OCD) having a high, a low and a high impedance (Hi-Z) state. The OCD includes an up-level pre-drive, a down-level pre-drive and a driver. The driver mirrors current in the up-level pre-drive and down-level pre-drive. Both pre-drive circuits have an unbalanced input-dependant delay to quickly turn off/on the on and off driver devices and, after a delay, reduce the drive on the turned on device to a steady state level. The delay may have a fixed length set by an inverter chain or may be dependent upon output voltage.
摘要翻译：具有高，低和高阻抗（Hi-Z）状态的片外驱动器（OCD）。 OCD包括上级预驱动，下级预驱动和驱动程序。驱动程序在上级预驱动和下级预驱动器中镜像当前。两个预驱动电路具有不平衡的输入相关延迟，以快速关闭/打开和关闭驱动器设备，并且在延迟之后将打开的设备上的驱动器减小到稳定状态级别。延迟可以具有由逆变器链设置的固定长度，或者可以取决于输出电压。

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