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1. 发明申请

US20120074559A1 INTEGRATED CIRCUIT PACKAGE USING THROUGH SUBSTRATE VIAS TO GROUND LID 审中-公开
标题翻译：使用通过基板VIAS的接地电路的集成电路封装
公开(公告)号：US20120074559A1
公开(公告)日：2012-03-29
申请号：US12889586
申请日：2010-09-24
申请人： Timothy W. Budell , Mark C.H. Lamorey , Peter Slota, JR.
发明人： Timothy W. Budell , Mark C.H. Lamorey , Peter Slota, JR.
IPC分类号： H01L23/29
CPC分类号： H01L23/055 , H01L23/42 , H01L23/481 , H01L23/552 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/15311 , H01L2924/16195 , H01L2924/00
摘要： An integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias. The stack of two or more integrated circuit chips is disposed within the metal lid and electrically mounted to the package substrate. An inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias. The TSVs provide electromagnetic interference shielding. A conductive thermal interface material may also be used. An alternative embodiment includes a single integrated circuit chip using TSVs to ground the metal lid.
摘要翻译：一种集成电路封装，其包括封装基板，安装到封装基板的金属盖，以及通过基板通孔彼此电连接的两个或多个集成电路芯片的堆叠。两个或多个集成电路芯片的堆叠被布置在金属盖内并电安装到封装基板。金属盖的顶部的内表面通过贯穿基板通孔与封装衬底中的接地线电连接。 TSV提供电磁干扰屏蔽。还可以使用导电热界面材料。一个替代实施例包括使用TSV来对金属盖进行接地的单个集成电路芯片。

2. 发明申请

US20100174503A1 Monitoring NFET/PFET Skew in Complementary Metal Oxide Semiconductor Devices 审中-公开
标题翻译：监测互补金属氧化物半导体器件中的NFET / PFET偏移
公开(公告)号：US20100174503A1
公开(公告)日：2010-07-08
申请号：US12349698
申请日：2009-01-07
申请人： Bruce Balch , Anthony Wayne Fazekas , Mark C.H. Lamorey , Jeffrey H. Oppold , Joseph James Oler, JR. , Chirstopher Daniel Parkinson
发明人： Bruce Balch , Anthony Wayne Fazekas , Mark C.H. Lamorey , Jeffrey H. Oppold , Joseph James Oler, JR. , Chirstopher Daniel Parkinson
IPC分类号： G01R29/02 , G21C17/00 , H03K3/03
CPC分类号： G01R31/2621 , G01R31/2648 , H01L22/34
摘要： An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance.
摘要翻译：在CMOS器件处理中用于直接测量NFET晶体管相对于PFET晶体管的性能偏移的装置包括一个环形振荡器，其频率用于测量随机跨越芯片变化以及跨芯片变化的相关性; 具有由环形振荡器驱动的输入的平衡逆变器，其中平衡逆变器被设计成形成为使得逆变器的一个或多个NFET器件的电流驱动能力基本上等于一个或多个PFET器件的电流驱动能力在给定的工作温度下; 以及耦合到反相器的输出的电容器，电容器两端的电压指示在NFET器件性能和PFET器件性能之间是否存在偏斜。

3. 发明申请

US20120318648A1 NORMALLY CLOSED MICROELECTROMECHANICAL SWITCHES (MEMS), METHODS OF MANUFACTURE AND DESIGN STRUCTURES 失效
标题翻译：正常关闭微电子开关（MEMS），制造方法和设计结构
公开(公告)号：US20120318648A1
公开(公告)日：2012-12-20
申请号：US13161126
申请日：2011-06-15
申请人： Dawn D. HALL , Mark C.H. LAMOREY , Anthony K. STAMPER
发明人： Dawn D. HALL , Mark C.H. LAMOREY , Anthony K. STAMPER
IPC分类号： H01H59/00 , G06F17/50 , H01H11/00
CPC分类号： H01H59/0009 , B81B2201/014 , G06F17/5068 , H01H11/00 , Y10T29/49105 , Y10T29/49117 , Y10T29/49155 , Y10T29/49204
摘要： Normally closed (shut) micro-electro-mechanical switches (MEMS), methods of manufacture and design structures are provided. A method of forming a micro-electrical-mechanical structure (MEMS), includes forming a plurality of electrodes on a substrate, forming a beam structure in electrical contact with a first of the electrodes, and bending the beam structure with a thermal process. The method further includes forming a cantilevered electrode extending over an end of the bent beam structure, and returning the beam structure to its original position, which will contact the cantilevered electrode in a normally closed position.
摘要翻译：提供常闭（关闭）微机电开关（MEMS），制造方法和设计结构。一种形成微机电结构（MEMS）的方法，包括在基板上形成多个电极，形成与第一电极电接触的光束结构，以及用热过程弯曲光束结构。该方法还包括形成在弯曲梁结构的一端延伸的悬臂电极，并将梁结构返回到其初始位置，其将在常闭位置接触悬臂电极。

4. 发明申请

US20140021622A1 OPTIMIZATION METALLIZATION FOR PREVENTION OF DIELECTRIC CRACKING UNDER CONTROLLED COLLAPSE CHIP CONNECTIONS 有权
标题翻译：优化金属化防止电磁破碎在控制的胶片连接
公开(公告)号：US20140021622A1
公开(公告)日：2014-01-23
申请号：US13553941
申请日：2012-07-20
申请人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C.H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
发明人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C.H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
IPC分类号： H01L23/52 , H01L21/60
CPC分类号： H01L23/53295 , H01L23/3192 , H01L23/522 , H01L23/5329 , H01L2224/0401 , H01L2224/05 , H01L2224/05567 , H01L2224/05572 , H01L2224/13 , H01L2224/13021 , H01L2924/00014 , H01L2924/3512 , H01L2224/05552
摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.
摘要翻译：一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。衬底包括用于C4的多个附接垫。该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

5. 发明申请

US20090282375A1 Circuit And Method Using Distributed Phase Change Elements For Across-Chip Temperature Profiling 有权
标题翻译：用于跨芯片温度分布的分布相变元件的电路和方法
公开(公告)号：US20090282375A1
公开(公告)日：2009-11-12
申请号：US12117784
申请日：2008-05-09
申请人： Nazmul Habib , Mark C.H. Lamorey , Thomas M. Maffitt , Robert McMahon
发明人： Nazmul Habib , Mark C.H. Lamorey , Thomas M. Maffitt , Robert McMahon
IPC分类号： G06F17/50 , G01K3/00
CPC分类号： G01K3/14 , G01K7/006 , G01K7/425
摘要： Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores.
摘要翻译：公开了一种跨芯片温度感测电路及其相关方法，可用于对片内温度梯度进行分析。这些实施例结合了大致均匀分布在半导体芯片上的多个相变元件。这些相变元件被编程为具有基本上相同的无定形电阻。每个相变元件单独表现出的温度相关行为与参考（例如，由离散参考相变元件产生，由另一个相变元件产生或由外部参考产生）相比较，以便描述半导体芯片上的温度梯度。一旦进行了分析，该温度梯度可用于重新设计和/或重新定位功能核心，为功能核心的鉴定和/或调整功能核心的操作规范设定应力限制。

6. 发明申请

US20120187953A1 CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT CHIP, METHODS OF USE AND MANUFACTURE AND DESIGN STRUCTURES 有权
标题翻译：用于检测集成电路芯片中的结构缺陷的电路，使用和制造方法和设计结构
公开(公告)号：US20120187953A1
公开(公告)日：2012-07-26
申请号：US13010057
申请日：2011-01-20
申请人： Luke D. LACROIX , Mark C.H. Lamorey , Steven F. Oakland , Janak G. Patel , Kerry P. Pfarr , Peter Slota, JR. , David B. Stone
发明人： Luke D. LACROIX , Mark C.H. Lamorey , Steven F. Oakland , Janak G. Patel , Kerry P. Pfarr , Peter Slota, JR. , David B. Stone
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/2896 , H01L21/76895 , H01L22/32
摘要： Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.
摘要翻译：本文提供了检测电路，使用和制造方法以及设计结构。该结构包括穿过集成电路的一个或多个金属层的至少一个信号线。电路耦合到所述至少一个信号线，其被构造为接收具有来自至少一个信号线的已知信号或来自不同电位的信号的信号，并且基于哪个信号被接收，确定是否存在集成电路中的结构缺陷。

7. 发明申请

US20110116312A1 NON VOLATILE CELL AND ARCHITECTURE WITH SINGLE BIT RANDOM ACCESS READ, PROGRAM AND ERASE 有权
标题翻译：非易失性单元和单个单元随机访问阅读，程序和删除的架构
公开(公告)号：US20110116312A1
公开(公告)日：2011-05-19
申请号：US12619771
申请日：2009-11-17
申请人： Chung H. Lam , Mark C.H. Lamorey , Thomas M. Maffitt
发明人： Chung H. Lam , Mark C.H. Lamorey , Thomas M. Maffitt
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10
摘要： One embodiment is a non-volatile memory cell with random access read, program, and erase. The memory cell includes a cell transistor that includes a source region, a drain region, a first insulating spacer, and a second insulating spacer. The memory cell also includes a source-side transistor, a drain-side transistor, a source-side multiplexer, a drain-side multiplexer, a source-side sense amplifier, and a drain-side write driver. A first binary value is stored in a first bit in the memory cell by trapping or releasing a first electric charge in the first insulating spacer. The first bit is read by sensing the resistive change in the cell transistor or by sensing the threshold voltage change in the cell transistor.
摘要翻译：一个实施例是具有随机访问读取，编程和擦除的非易失性存储单元。存储单元包括一个单元晶体管，它包括一个源极区，一个漏极区，一个第一绝缘间隔物和一个第二绝缘隔离物。存储单元还包括源极晶体管，漏极侧晶体管，源极侧多路复用器，漏极侧多路复用器，源极侧读出放大器和漏极侧写入驱动器。通过在第一绝缘间隔物中捕获或释放第一电荷，将第一二进制值存储在存储器单元中的第一位中。通过感测单元晶体管中的电阻变化或通过感测单元晶体管中的阈值电压变化来读取第一位。

8. 发明申请

US20140033148A1 ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE 失效
标题翻译：芯片包装中的芯片载体的弹性模块映射
公开(公告)号：US20140033148A1
公开(公告)日：2014-01-30
申请号：US13557386
申请日：2012-07-25
申请人： Erwin B. Cohen , Mark C.H. Lamorey , Marek A. Orlowski , Douglas O. Powell , David L. Questad , David B. Stone , Paul R. Walling
发明人： Erwin B. Cohen , Mark C.H. Lamorey , Marek A. Orlowski , Douglas O. Powell , David L. Questad , David B. Stone , Paul R. Walling
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.
摘要翻译：计算机实现的方法提供了倒装芯片封装的芯片载体的弹性模量图。将包括芯片载体的每个层的每个垂直对准子区域的电介质和导电设计元件的设计数据建模为弹簧以提供弹性模量图。确定芯片载体的子区域的弹性模量在芯片接合期间识别可能的机械故障位置并冷却倒装芯片封装。将焊料凸块修改为芯片载体可以减少施加到识别的可能的机械故障位置的应力。修改芯片载体设计以减少与识别出的可能的机械故障位置相关联的子区域的刚度，还可减少芯片连接和冷却的应力。

9. 发明申请

US20090086534A1 APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES 失效
标题翻译：用于实施PCRAM设备精密感测的装置和方法
公开(公告)号：US20090086534A1
公开(公告)日：2009-04-02
申请号：US11865134
申请日：2007-10-01
申请人： John K. DeBrosse , Thomas M. Maffitt , Mark C.H. Lamorey
发明人： John K. DeBrosse , Thomas M. Maffitt , Mark C.H. Lamorey
IPC分类号： G11C11/00 , G11C7/00 , G11C7/10
CPC分类号： G11C29/02 , G11C7/062 , G11C7/067 , G11C13/0004 , G11C13/004 , G11C29/026 , G11C29/028 , G11C2013/0054
摘要： A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.
摘要翻译：精密读出放大器装置包括：电流源，被配置为通过参考支路引入可调参考电流; 配置为将参考电流镜像到数据支路的电流镜，所述数据支路选择性地耦合到可编程电阻存储元件; 耦合到所述数据支脚的有源钳位装置，并且被配置为在所述存储元件上钳位固定电压，由此建立其固定的电流吸收能力; 以及差分读出放大器，其具有耦合到所述数据支路的第一输入端和耦合到所述基准支路的第二输入端; 其中每当所述参考电流小于所述存储元件的固定电流吸收能力时，所述差分读出放大器的输出呈现第一逻辑状态，并且每当所述参考电流超过所述固定电流吸收能力时，所述差分读出放大器的输出呈现第二逻辑状态。

10. 发明申请

US20080229269A1 DESIGN STRUCTURE FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES 审中-公开
标题翻译：在SRAM器件中集成非易失性存储器容量的设计结构
公开(公告)号：US20080229269A1
公开(公告)日：2008-09-18
申请号：US11849550
申请日：2007-09-04
申请人： Mark C.H. Lamorey
发明人： Mark C.H. Lamorey
IPC分类号： G06F17/50
CPC分类号： G11C14/0081
摘要： A design structure embodied in a machine readable medium used in a design process includes a nonvolatile static random access memory (SRAM) device, including a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data; and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell; wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括非易失性静态随机存取存储器（SRAM）器件，其包括一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，其配置为用于位的存储单元数据的; 以及耦合到所述存储单元的相对侧的一对磁性自旋转移装置; 其中所述磁自旋转移装置被配置为在去除所述SRAM装置的电力之后将所述存储单元数据保持在其中，并且还被配置为在向所述SRAM装置施加电力时利用所述保留的数据初始化所述存储单元。

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