专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090090961A1 Non-Volatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090090961A1
公开(公告)日：2009-04-09
申请号：US12246193
申请日：2008-10-06
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

2. 发明授权

US08492826B2 Non-volatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08492826B2
公开(公告)日：2013-07-23
申请号：US12782378
申请日：2010-05-18
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L27/11568 , H01L29/66833
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

3. 发明授权

US08000137B2 Nonvolatile semiconductor memory device and usage method thereof 有权
标题翻译：非易失性半导体存储器件及其使用方法
公开(公告)号：US08000137B2
公开(公告)日：2011-08-16
申请号：US12400015
申请日：2009-03-09
申请人： Taku Ogura , Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Yoshiki Kawajiri , Masaaki Mihara
发明人： Taku Ogura , Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Yoshiki Kawajiri , Masaaki Mihara
IPC分类号： G11C16/04
CPC分类号： G11C16/045 , G11C16/0441 , G11C16/12 , G11C2216/10 , H01L27/11521 , H01L27/11558
摘要： A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.
摘要翻译：非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

4. 发明申请

US20090244972A1 Nonvolatile Semiconductor Memory Device and Usage Method Thereof 有权
标题翻译：非易失性半导体存储器件及其使用方法
公开(公告)号：US20090244972A1
公开(公告)日：2009-10-01
申请号：US12400015
申请日：2009-03-09
申请人： Taku Ogura , Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Yoshiki Kawajiri , Masaaki Mihara
发明人： Taku Ogura , Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Yoshiki Kawajiri , Masaaki Mihara
IPC分类号： G11C14/00 , G11C16/04 , G11C7/06
CPC分类号： G11C16/045 , G11C16/0441 , G11C16/12 , G11C2216/10 , H01L27/11521 , H01L27/11558
摘要： A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.
摘要翻译：非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

5. 发明授权

US08106443B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08106443B2
公开(公告)日：2012-01-31
申请号：US12246193
申请日：2008-10-06
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

6. 发明申请

US20100283099A1 Non-Volatile Semiconductor Memory Device and Manufacturing Method Thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100283099A1
公开(公告)日：2010-11-11
申请号：US12782378
申请日：2010-05-18
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L27/11568 , H01L29/66833
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域平行于所述肋的纵向方向，形成在所述沟槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

7. 发明申请

US20090175083A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090175083A1
公开(公告)日：2009-07-09
申请号：US11684035
申请日：2007-03-09
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

8. 发明申请

US20120014181A1 Nonvolatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20120014181A1
公开(公告)日：2012-01-19
申请号：US13205900
申请日：2011-08-09
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C16/10 , G11C16/28 , G11C16/04
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

9. 发明授权

US07701778B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07701778B2
公开(公告)日：2010-04-20
申请号：US11684035
申请日：2007-03-09
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C11/34
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

10. 发明授权

US07573742B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07573742B2
公开(公告)日：2009-08-11
申请号：US11550335
申请日：2006-10-17
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行位数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式