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1. 发明授权

US5914522A Power semiconductor structure with lateral transistor driven by vertical transistor 失效
标题翻译：功率半导体结构，横向晶体管由垂直晶体管驱动
公开(公告)号：US5914522A
公开(公告)日：1999-06-22
申请号：US859024
申请日：1997-05-20
申请人： Natale Aiello , Davide Patti , Salvatore Leonardi , Salvatore Scaccianoce
发明人： Natale Aiello , Davide Patti , Salvatore Leonardi , Salvatore Scaccianoce
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8224 , H01L21/8228 , H01L21/8249 , H01L27/06 , H01L27/07 , H01L27/082 , H01L29/732 , H01L29/00 , H01L27/102
CPC分类号： H01L27/0821 , H01L27/0722
摘要： A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.
摘要翻译：一种功率半导体结构（200），特别是在VIPower技术中，由N型半导体材料（110）的芯片制成，包括具有集电极或漏极的双极或场效应垂直功率晶体管（125,120,110）这种N型材料（110）中的区域; 该半导体结构包括PNP双极侧向功率晶体管（210,110,220），其具有基本上与垂直功率晶体管的集电极或漏极区共同的N型材料（110）中的基极区域。

2. 发明授权

US06518139B1 Power semiconductor device structure with vertical PNP transistor 有权
标题翻译：功率半导体器件结构采用垂直PNP晶体管
公开(公告)号：US06518139B1
公开(公告)日：2003-02-11
申请号：US09569277
申请日：2000-05-11
申请人： Natale Aiello , Davide Patti , Salvatore Scaccianoce , Salvatore Leonardi
发明人： Natale Aiello , Davide Patti , Salvatore Scaccianoce , Salvatore Leonardi
IPC分类号： H01L218224
CPC分类号： H01L27/0821 , H01L21/8224
摘要： A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region including of a buried region between the substrate and the epitaxial layer and a contact region. The P region delimits a base N region within which an emitter P region is formed.
摘要翻译：形成在半导体材料芯片中的功率半导体器件结构包括N型衬底和N型外延层。该结构包括形成其中形成控制电路的口袋的P型绝缘区域和多个完全绝缘的PNP功率晶体管。每个PNP功率晶体管包括P型集电极区域，其包括在衬底和外延层之间的掩埋区域和接触区域。 P区域限定形成发射极P区域的基极N区域。

3. 发明授权

US5830783A Monolithic semiconductor device having an edge structure and method for producing said structure 失效
标题翻译：具有边缘结构的单片半导体器件及其制造方法
公开(公告)号：US5830783A
公开(公告)日：1998-11-03
申请号：US758571
申请日：1996-12-03
申请人： Natale Aiello , Atanasio LaBarbera , Salvatore Leonardi
发明人： Natale Aiello , Atanasio LaBarbera , Salvatore Leonardi
IPC分类号： H01L21/761 , H01L27/06 , H01L21/332 , H01L21/8236
CPC分类号： H01L21/761 , H01L27/0629
摘要： A monolithic semiconductor device having an edge structure that facilitates integrating high power devices an logic devices on the same substrate. The semiconductor device includes on a substrate of a first type of doping, a control region of a second type of doping, which is provided with an edge region, and a power region of a second type of doping. In the edge region, at least one channel is provided which is adapted to divide the edge region into regions that are electrically isolated from each other, the region at the channel being covered with a field plate. A method for producing such an edge structure in combination with the production execution of the monolithic device is also disclosed herein.
摘要翻译：具有边缘结构的单片半导体器件，其有助于将高功率器件集成在同一衬底上的逻辑器件。半导体器件包括在第一类型的掺杂的衬底上，具有边缘区域的第二类型掺杂的控制区域和第二类型掺杂的功率区域。在边缘区域中，提供至少一个通道，其适于将边缘区域划分为彼此电隔离的区域，通道处的区域被场板覆盖。本文还公开了与单片装置的生产执行相结合来生产这种边缘结构的方法。

4. 发明授权

US06441445B1 Integrated device with bipolar transistor and electronic switch in “emitter switching” configuration 有权
标题翻译：具有双极晶体管和电子开关的“发射极开关”配置的集成器件
公开(公告)号：US06441445B1
公开(公告)日：2002-08-27
申请号：US09413740
申请日：1999-10-06
申请人： Salvatore Leonardi , Davide Patti , Delfo Sanfilippo
发明人： Salvatore Leonardi , Davide Patti , Delfo Sanfilippo
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L21/823462
摘要： The integrated circuit device has a vertical conduction structure in which a region, which contains the base of a bipolar transistor, has zones having different concentrations. The concentrations are lower where the flow of charges is more intense and higher elsewhere. A high gain of the bipolar transistor and a low resistance of the electronic switch in conduction are thus obtained.
摘要翻译：集成电路器件具有垂直导电结构，其中包含双极晶体管的基极的区域具有不同浓度的区域。在电荷流动更强烈和其他地方较高的地方，浓度较低。因此获得双极晶体管的高增益和电子开关在导通中的低电阻。

5. 发明授权

US08575720B2 Process for integrating on an inert substrate a device comprising at least a passive element and an active element and corresponding integrated device 有权
标题翻译：用于在惰性基板上集成至少包括无源元件和有源元件的器件以及相应的集成器件的工艺
公开(公告)号：US08575720B2
公开(公告)日：2013-11-05
申请号：US11803716
申请日：2007-05-14
申请人： Salvatore Leonardi , Salvatore Coffa , Claudia Caligiore , Francesca Paola Tramontana
发明人： Salvatore Leonardi , Salvatore Coffa , Claudia Caligiore , Francesca Paola Tramontana
IPC分类号： H01L27/08
CPC分类号： H01L21/84 , H01L27/12
摘要： A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.
摘要翻译：描述了一种在惰性基板上集成具有至少一个无源部件和一个有源部件的装置的方法。该方法包括：将保护电介质层沉积在惰性衬底上; 在保护电介质层上形成多晶硅岛; 有源元件在多晶硅岛上的集成; 覆盖电介质层沉积在保护电介质层和有源元件上; 将被动元件集成在覆盖介电层上; 在与所述有源部件的有源区域对应的覆盖介电层中实现的开口中形成第一接触结构; 以及与被动部件对应地形成第二接触结构。还描述了通过该方法获得的集成装置。

6. 发明授权

US07952104B2 Thin-film transistor (TFT) device 有权
标题翻译：薄膜晶体管（TFT）器件
公开(公告)号：US07952104B2
公开(公告)日：2011-05-31
申请号：US12564719
申请日：2009-09-22
申请人： Salvatore Leonardi , Claudia Caligiore
发明人： Salvatore Leonardi , Claudia Caligiore
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L21/02686 , H01L21/02488 , H01L21/02532 , H01L21/2026 , H01L27/1229 , H01L27/1281 , H01L29/66757
摘要： A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.
摘要翻译：一种薄膜晶体管器件的制造方法，其特征在于，在基板上形成介电绝缘层，在所述绝缘层上形成非晶硅层，使所述非晶硅层结晶化，得到多晶硅，在所述多晶硅上形成栅极结构硅，并且相对于栅极结构横向地在多晶硅内形成第一掺杂区域。所述结晶步骤包括在所述非晶硅层上形成第一覆盖电介质区域，然后使用激光照射所述非晶硅层，以便形成由所述第一覆盖电介质区域下方的非晶硅的分离部分分离的多晶硅的有源区域。

7. 发明申请

US20100163759A1 RADIATION SENSOR WITH PHOTODIODES BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING INTEGRATION PROCESS 审中-公开
标题翻译：带有光电转换器的辐射传感器集成在半导体衬底和相应的集成工艺
公开(公告)号：US20100163759A1
公开(公告)日：2010-07-01
申请号：US12649256
申请日：2009-12-29
申请人： Maria Eloisa Castagna , Salvatore Leonardi , Salvatore Abbisso , Lidia Maddiona
发明人： Maria Eloisa Castagna , Salvatore Leonardi , Salvatore Abbisso , Lidia Maddiona
IPC分类号： H01L31/14 , H01L31/0216 , H01L31/18
CPC分类号： H01L31/18 , G01J1/0488 , G01J1/4204 , G01J1/4228 , H01L27/1443 , H01L31/02165
摘要： An embodiment relates to a sensor integrated on a semiconductor substrate and comprising at least one first and second photodiode including at least one first and one second p-n junction made in such a semiconductor substrate as well as at least one first and one second antireflection coating made on top of such a first and second photodiode. At least one antireflection coating of such a first and second photodiode comprises at least one first and one second different antireflection layer to make a double layer antireflection coating suitable for obtaining for the corresponding photodiode a responsivity peak at a predetermined wavelength of an optical signal incident on the sensor. An embodiment also refers to an integration process of such a sensor, as well as to an ambient light sensor made with such a sensor.
摘要翻译：实施例涉及集成在半导体衬底上并包括至少一个第一和第二光电二极管的传感器，该至少一个第一和第二光电二极管包括在这种半导体衬底中形成的至少一个第一和一个第二pn结，以及至少一个第一和第二反射防止涂层这样的第一和第二光电二极管的顶部。这种第一和第二光电二极管的至少一个抗反射涂层包括至少一个第一和第二不同的抗反射层，以制造双层抗反射涂层，其适合于为相应的光电二极管获得在入射到其上的光信号的预定波长的响应峰传感器。实施例还涉及这种传感器以及由这种传感器制成的环境光传感器的集成过程。

8. 发明申请

US20070148527A1 FUEL CELL PLANARLY INTEGRATED ON A MONOCRYSTALLINE SILICON CHIP AND PROCESS OF FABRICATION 有权
标题翻译：燃料电池平面集成在单晶硅芯片和制造工艺
公开(公告)号：US20070148527A1
公开(公告)日：2007-06-28
申请号：US11611521
申请日：2006-12-15
申请人： Simone Siciliano , Luigi La Magna , Salvatore Leonardi
发明人： Simone Siciliano , Luigi La Magna , Salvatore Leonardi
IPC分类号： H01M8/02 , H01M4/86 , H01M4/88 , B05D5/12 , C25D5/02 , C25D3/00
CPC分类号： H01M8/1097 , H01M8/0271 , H01M8/04089 , H01M8/241 , H01M8/2425 , H01M2008/1095
摘要： A fuel cell is entirely fabricated on a single monocrystalline silicon substrate, and substantially overcomes leak proofing and wafer bonding difficulties and criticalities while ensuring an intrinsic sturdiness of the planarly integrated functional structure of the fuel cell. The integrated fuel cell is formed in an oxidized porous silicon region on a monocrystalline silicon substrate that is pervious to fluid flow and is electrically nonconductive with the monocrystalline silicon substrate.
摘要翻译：燃料电池完全制造在单个单晶硅衬底上，并且基本上克服了防漏和晶片接合困难和临界，同时确保燃料电池的平面集成的功能结构的内在坚固性。集成的燃料电池形成在单晶硅衬底上的氧化的多孔硅区域中，该单晶硅衬底可渗透流体流动并且与单晶硅衬底不导电。

9. 发明申请

US20070034872A1 Process for manufacturing a thin-film transistor (TFT) device and TFT device manufactured by the process 有权
标题翻译：用于制造薄膜晶体管（TFT）器件和通过该工艺制造的TFT器件的工艺
公开(公告)号：US20070034872A1
公开(公告)日：2007-02-15
申请号：US11478332
申请日：2006-06-28
申请人： Salvatore Leonardi , Claudia Caligiore
发明人： Salvatore Leonardi , Claudia Caligiore
IPC分类号： H01L29/04
CPC分类号： H01L21/02686 , H01L21/02488 , H01L21/02532 , H01L21/2026 , H01L27/1229 , H01L27/1281 , H01L29/66757
摘要： A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.
摘要翻译：一种薄膜晶体管器件的制造方法，其特征在于，在基板上形成介电绝缘层，在所述绝缘层上形成非晶硅层，使所述非晶硅层结晶化，得到多晶硅，在所述多晶硅上形成栅极结构硅，并且相对于栅极结构横向地在多晶硅内形成第一掺杂区域。所述结晶步骤包括在所述非晶硅层上形成第一覆盖电介质区域，然后使用激光照射所述非晶硅层，以便形成由所述第一覆盖电介质区域下方的非晶硅的分离部分分离的多晶硅的有源区域。

10. 发明授权

US06815795B2 High voltage resistive structure integrated on a semiconductor substrate 有权
标题翻译：集成在半导体衬底上的高电压电阻结构
公开(公告)号：US06815795B2
公开(公告)日：2004-11-09
申请号：US10420386
申请日：2003-04-21
申请人： Salvatore Leonardi
发明人： Salvatore Leonardi
IPC分类号： H01L2900
CPC分类号： H01L21/76208 , H01L21/761 , H01L27/0802
摘要： A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

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