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1. 发明授权

US09570166B1 Read operations and circuits for memory devices having programmable elements, including programmable resistance elements 有权
标题翻译：读取具有可编程元件的存储器件的操作和电路，包括可编程电阻元件
公开(公告)号：US09570166B1
公开(公告)日：2017-02-14
申请号：US14572646
申请日：2014-12-16
申请人： Nad Edward Gilbert , Ishai Naveh , Narbeh Derhacobian
发明人： Nad Edward Gilbert , Ishai Naveh , Narbeh Derhacobian
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/004 , G11C7/06 , G11C11/56 , G11C11/5614 , G11C13/0002 , G11C13/0011 , G11C16/26 , G11C2013/0054 , G11C2013/0057
摘要： A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.
摘要翻译：存储器件和方法可以使用多重检测操作来检测处于边缘状态的存储器元件的状态。在一些实施例中，评估电路可以响应于相同存储器元件的多个感测结果而产生用于存储器元件的输出值。

2. 发明授权

US08947913B1 Circuits and methods having programmable impedance elements 有权
标题翻译：具有可编程阻抗元件的电路和方法
公开(公告)号：US08947913B1
公开(公告)日：2015-02-03
申请号：US13114192
申请日：2011-05-24
申请人： Narbeh Derhacobian , Ishai Naveh
发明人： Narbeh Derhacobian , Ishai Naveh
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0023 , G11C13/003 , G11C13/0035 , G11C14/009 , G11C2213/53 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L45/085
摘要： Integrated circuit (IC) devices are disclosed that include programmable impedance elements (elements) as data storage element. In some embodiments, IC devices can include latch circuit with one or more elements that establish a function of an associated circuit. In other embodiments, IC devices can include elements arranged in a cross-point array connected to control terminals of access devices. In still other embodiments, a memory device can include a programmable address decoder. Corresponding methods are also disclosed.
摘要翻译：公开了包括可编程阻抗元件（元件）作为数据存储元件的集成电路（IC）器件。在一些实施例中，IC器件可以包括具有建立相关电路功能的一个或多个元件的锁存电路。在其他实施例中，IC器件可以包括布置在连接到接入设备的控制终端的交叉点阵列中的元件。在其他实施例中，存储器设备可以包括可编程地址解码器。还公开了相应的方法。

3. 发明授权

US08913444B1 Read operations and circuits for memory devices having programmable elements, including programmable resistance elements 有权
标题翻译：读取具有可编程元件的存储器件的操作和电路，包括可编程电阻元件
公开(公告)号：US08913444B1
公开(公告)日：2014-12-16
申请号：US13408797
申请日：2012-02-29
申请人： Nad Edward Gilbert , Ishai Naveh , Narbeh Derhacobian
发明人： Nad Edward Gilbert , Ishai Naveh , Narbeh Derhacobian
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/06 , G11C11/56 , G11C11/5614 , G11C13/0002 , G11C13/0011 , G11C16/26 , G11C2013/0054 , G11C2013/0057
摘要： A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.
摘要翻译：存储器件和方法可以使用多重检测操作来检测处于边缘状态的存储器元件的状态。在一些实施例中，评估电路可以响应于相同存储器元件的多个感测结果而产生用于存储器元件的输出值。在其他实施例中，存储器设备可以包括标准读取操作和强读操作，其中强读操作对于所选择的存储器元件比标准读操作应用更多的能量。

4. 发明授权

US08687403B1 Circuits having programmable impedance elements 有权
标题翻译：具有可编程阻抗元件的电路
公开(公告)号：US08687403B1
公开(公告)日：2014-04-01
申请号：US13157713
申请日：2011-06-10
申请人： Narbeh Derhacobian , Shane Charles Hollmer , Ishai Naveh
发明人： Narbeh Derhacobian , Shane Charles Hollmer , Ishai Naveh
IPC分类号： G11C11/00
CPC分类号： H01L45/085 , G11C11/005 , G11C13/0007 , G11C13/0011 , G11C14/0045 , G11C14/009
摘要： An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.
摘要翻译：集成电路（IC）装置可以包括具有多个易失性存储器单元的第一部分; 以及第二部分，其通过数据传输路径耦合到所述第一部分，所述第二部分包括多个非易失性存储器单元，每个非易失性存储单元包括在不同电阻值之间不止一次可编程的至少一个电阻元件。存储器件还可以包括可由存取双极结型晶体管（BJT）访问的可变阻抗元件，其中至少一部分由形成在衬底上的半导体层形成。存储器件还可以包括多个存储器元件，每个存储器元件包括形成在第一和第二电极之间的电介质层，该电介质层包括具有小于二硫化锗中银的迁移率的可溶性金属的固体电解质。

5. 发明申请

US20090212342A1 Asymmetric Single Poly NMOS Non-Volatile Memory Cell 有权
标题翻译：非对称单个多晶硅非易失性存储器单元
公开(公告)号：US20090212342A1
公开(公告)日：2009-08-27
申请号：US12037051
申请日：2008-02-25
申请人： Yakov Roizin , Evgeny Pikhay , Ishai Naveh
发明人： Yakov Roizin , Evgeny Pikhay , Ishai Naveh
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , G11C16/10 , H01L21/28273 , H01L21/823418 , H01L21/823462 , H01L27/088 , H01L27/0922 , H01L27/11546 , H01L29/42324 , H01L29/7881
摘要： An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.
摘要翻译：用于通过标准CMOS工艺流程形成的CMOS IC的非对称非易失性存储器（NVM）单元，用于在衬底上形成低电压和高压晶体管。 NVM单元包括NMOS浮栅晶体管和可选的选择晶体管。浮置栅极晶体管包括细长的浮动栅极，其具有设置在沟道区域C150上的第一部分，延伸到远离沟道区域的扩大的漏极扩散区域D150中的第二部分，由此栅极 - 漏极电容高于栅极到源极电容。浮动栅极延伸部分的宽度最小化，同时HV LDD和LV LDD植入物都被引入到一起，使LDD植入物在浮动栅极延伸部分下合并。 NV LD晶体管中的HV LDD注入被LV LDD所取代。浮动栅极使用大致U形或J形多晶硅结构形成。公开了各种阵列寻址方案。

6. 发明授权

US08902631B2 Memory devices, circuits and, methods that apply different electrical conditions in access operations 有权
标题翻译：存储器件，电路和在接入操作中应用不同电气条件的方法
公开(公告)号：US08902631B2
公开(公告)日：2014-12-02
申请号：US13600161
申请日：2012-08-30
申请人： Ravi Sunkavalli , Ishai Naveh , Malcolm Wing
发明人： Ravi Sunkavalli , Ishai Naveh , Malcolm Wing
IPC分类号： G11C11/00
CPC分类号： G11C11/225 , G11C8/12 , G11C11/165 , G11C11/22 , G11C11/2275 , G11C13/0002 , G11C13/0004 , G11C13/0011 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C16/3495 , G11C2029/0411
摘要： A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.
摘要翻译：存储器设备可以包括多个物理块，每个物理块包括可在至少两个不同阻抗状态之间可编程的多个存储器元件，存储器元件遭受性能下降; 以及偏置电路，被配置为将愈合电气条件应用于不包含有效数据的至少一个备用物理块; 其中所述愈合电气条件不同于写入操作电气条件，以及所述至少一个备用物理块的存储器元件的反向劣化。

7. 发明申请

US20100027346A1 Asymmetric Single Poly NMOS Non-Volatile Memory Cell 审中-公开
公开(公告)号：US20100027346A1
公开(公告)日：2010-02-04
申请号：US12582627
申请日：2009-10-20
申请人： Yakov Roizin , Evgeny Pikhay , Ishai Naveh
发明人： Yakov Roizin , Evgeny Pikhay , Ishai Naveh
IPC分类号： G11C16/04 , H01L29/788 , G11C5/14
CPC分类号： H01L27/11526 , G11C16/10 , H01L21/823418 , H01L21/823462 , H01L27/088 , H01L27/0922 , H01L27/11546 , H01L29/40114 , H01L29/42324 , H01L29/7881
摘要： An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.

8. 发明申请

US20140063902A1 MEMORY DEVICES, CIRCUITS AND, METHODS THAT APPLY DIFFERENT ELECTRICAL CONDITIONS IN ACCESS OPERATIONS 有权
标题翻译：记忆装置，电路和方法，适用于不同的电气条件进入操作
公开(公告)号：US20140063902A1
公开(公告)日：2014-03-06
申请号：US13600161
申请日：2012-08-30
申请人： Ravi Sunkavalli , Ishai Naveh , Malcolm Wing
发明人： Ravi Sunkavalli , Ishai Naveh , Malcolm Wing
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C11/225 , G11C8/12 , G11C11/165 , G11C11/22 , G11C11/2275 , G11C13/0002 , G11C13/0004 , G11C13/0011 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C16/3495 , G11C2029/0411
摘要： A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.
摘要翻译：存储器设备可以包括多个物理块，每个物理块包括可在至少两个不同阻抗状态之间可编程的多个存储器元件，存储器元件遭受性能下降; 以及偏置电路，被配置为将愈合电气条件应用于不包含有效数据的至少一个备用物理块; 其中所述愈合电气条件不同于写入操作电气条件，以及所述至少一个备用物理块的存储器元件的反向劣化。

9. 发明授权

US07948020B2 Asymmetric single poly NMOS non-volatile memory cell 有权
标题翻译：不对称单个多晶硅非易失性存储单元
公开(公告)号：US07948020B2
公开(公告)日：2011-05-24
申请号：US12730176
申请日：2010-03-23
申请人： Yakov Roizin , Evgeny Pikhay , Ishai Naveh
发明人： Yakov Roizin , Evgeny Pikhay , Ishai Naveh
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , G11C16/10 , H01L21/28273 , H01L21/823418 , H01L21/823462 , H01L27/088 , H01L27/0922 , H01L27/11546 , H01L29/42324 , H01L29/7881
摘要： An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.
摘要翻译：用于通过标准CMOS工艺流程形成的CMOS IC的非对称非易失性存储器（NVM）单元，用于在衬底上形成低电压和高压晶体管。 NVM单元包括NMOS浮栅晶体管和可选的选择晶体管。浮置栅极晶体管包括细长的浮动栅极，其具有设置在沟道区域C150上的第一部分，延伸到远离沟道区域的扩大的漏极扩散区域D150中的第二部分，由此栅极 - 漏极电容高于栅极到源极电容。浮动栅极延伸部分的宽度最小化，同时HV LDD和LV LDD植入物都被引入到一起，使LDD植入物在浮动栅极延伸部分下合并。 NV LD晶体管中的HV LDD注入被LV LDD所取代。浮动栅极使用大致U形或J形多晶硅结构形成。公开了各种阵列寻址方案。

10. 发明授权

US07800156B2 Asymmetric single poly NMOS non-volatile memory cell 有权
标题翻译：不对称单个多晶硅非易失性存储单元
公开(公告)号：US07800156B2
公开(公告)日：2010-09-21
申请号：US12037051
申请日：2008-02-25
申请人： Yakov Roizin , Evgeny Pikhay , Ishai Naveh
发明人： Yakov Roizin , Evgeny Pikhay , Ishai Naveh
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , G11C16/10 , H01L21/28273 , H01L21/823418 , H01L21/823462 , H01L27/088 , H01L27/0922 , H01L27/11546 , H01L29/42324 , H01L29/7881
摘要： An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.
摘要翻译：用于通过标准CMOS工艺流程形成的CMOS IC的非对称非易失性存储器（NVM）单元，用于在衬底上形成低电压和高压晶体管。 NVM单元包括NMOS浮栅晶体管和可选的选择晶体管。浮置栅极晶体管包括细长的浮动栅极，其具有设置在沟道区域C150上的第一部分，延伸到远离沟道区域的扩大的漏极扩散区域D150中的第二部分，由此栅极 - 漏极电容高于栅极到源极电容。浮动栅极延伸部分的宽度最小化，同时HV LDD和LV LDD植入物都被引入到一起，使LDD植入物在浮动栅极延伸部分下合并。 NV LD晶体管中的HV LDD注入被LV LDD所取代。浮动栅极使用大致U形或J形多晶硅结构形成。公开了各种阵列寻址方案。

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