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1. 发明授权

US08399356B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08399356B2
公开(公告)日：2013-03-19
申请号：US12408375
申请日：2009-03-20
申请人： Naoya Sakamoto , Takahiro Sato , Yoshiaki Oikawa , Rai Sato , Yamato Aihara , Takayuki Cho , Masami Jintyou
发明人： Naoya Sakamoto , Takahiro Sato , Yoshiaki Oikawa , Rai Sato , Yamato Aihara , Takayuki Cho , Masami Jintyou
IPC分类号： H01L21/306
CPC分类号： G06K19/07749 , G06K19/07779 , G06K19/07783 , H01L21/32134 , H01L21/32136 , H01L21/76829 , H01L21/76838 , H01L23/53223 , H01L27/124 , H01L27/1266 , H01L27/13 , H01L2924/0002 , H01L2924/00
摘要： A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 μm and equal to or less than 10 μm is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 μm and equal to or less than 10 μm to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.
摘要翻译：通过湿式蚀刻将厚度等于或大于1μm且等于或小于10μm的铝或铝合金的导电膜蚀刻成预定厚度，然后通过干法蚀刻进行蚀刻，可以抑制导电膜的蚀刻，并且可以抑制掩模的厚度减小。导电膜的侧蚀刻的抑制和掩模的厚度减小的抑制使得能够将具有等于或大于1μm并且等于或小于10μm的大的厚度的含有铝或铝合金的导电膜与被蚀刻使得导电膜的边缘部分的梯度可以陡峭，可以获得预定厚度的导电膜，并且可以抑制与掩模图案的形状差异。

2. 发明申请

US20090305503A1 Manufacturing Method of Semiconductor Device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20090305503A1
公开(公告)日：2009-12-10
申请号：US12408375
申请日：2009-03-20
申请人： Naoya Sakamoto , Takahiro Sato , Yoshiaki Oikawa , Rai Sato , Yamato Aihara , Takayuki Cho , Masami Jintyou
发明人： Naoya Sakamoto , Takahiro Sato , Yoshiaki Oikawa , Rai Sato , Yamato Aihara , Takayuki Cho , Masami Jintyou
IPC分类号： H01L21/306
CPC分类号： G06K19/07749 , G06K19/07779 , G06K19/07783 , H01L21/32134 , H01L21/32136 , H01L21/76829 , H01L21/76838 , H01L23/53223 , H01L27/124 , H01L27/1266 , H01L27/13 , H01L2924/0002 , H01L2924/00
摘要： A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 μm and equal to or less than 10 μm is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 μm and equal to or less than 10 μm to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.
摘要翻译：通过湿式蚀刻将厚度等于或大于1μm且等于或小于10μm的铝或铝合金的导电膜蚀刻成预定厚度，然后通过干法蚀刻进行蚀刻，可以抑制导电膜的蚀刻，并且可以抑制掩模的厚度减小。导电膜的侧蚀刻的抑制和掩模的厚度减小的抑制使得能够使含有铝或铝合金的导电膜即使具有等于或大于1μm以上并且等于或小于10μm的厚度被蚀刻使得导电膜的边缘部分的梯度可以陡峭，可以获得预定厚度的导电膜，并且可以抑制与掩模图案的形状差异。

3. 发明申请

US20110062432A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110062432A1
公开(公告)日：2011-03-17
申请号：US12879635
申请日：2010-09-10
申请人： Shunpei Yamazaki , Masayuki Sakakura , Jun Koyama , Yoshiaki Oikawa , Hotaka Maruyama , Masami Jintyou , Kenichi Okazaki
发明人： Shunpei Yamazaki , Masayuki Sakakura , Jun Koyama , Yoshiaki Oikawa , Hotaka Maruyama , Masami Jintyou , Kenichi Okazaki
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869 , H01L27/1225
摘要： An object is to realize low power consumption while manufacturing a semiconductor device including a thin film transistor whose parasitic capacitance is reduced. Part of an insulating layer covering the periphery of a gate electrode layer is formed to be thick. Specifically, a stack including a spacer insulating layer and a gate insulating layer is formed. The thick part of the insulating layer covering the periphery of the gate electrode layer reduces parasitic capacitance formed between the gate electrode layer of the thin film transistor and another electrode layer (another wiring layer) overlapping with the gate electrode layer.
摘要翻译：目的是在制造包括其寄生电容减小的薄膜晶体管的半导体器件的同时实现低功耗。覆盖栅电极层周围的绝缘层的一部分形成为较厚。具体地，形成包括间隔绝缘层和栅极绝缘层的堆叠。覆盖栅电极层周围的绝缘层的厚部减小了在薄膜晶体管的栅电极层与与栅电极层重叠的另一电极层（另一布线层）之间形成的寄生电容。

4. 发明申请

US20090261414A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090261414A1
公开(公告)日：2009-10-22
申请号：US12423563
申请日：2009-04-14
申请人： Yoshiaki Oikawa , Masayuki Kajiwara , Masataka Nakada , Masami Jintyou , Shunpei Yamazaki
发明人： Yoshiaki Oikawa , Masayuki Kajiwara , Masataka Nakada , Masami Jintyou , Shunpei Yamazaki
IPC分类号： H01L29/786 , H01L21/768 , H01L21/56
CPC分类号： H01L27/1266 , H01L21/568 , H01L23/3107 , H01L23/3114 , H01L27/1214 , H01L29/78606 , H01L29/78666 , H01L29/78669 , H01L2924/0002 , H01L2924/12044 , H01L2924/19041 , H01L2924/00
摘要： An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
摘要翻译：本发明的目的是通过降低膜的剥离度来提高半导体器件的耐水性和可靠性。在半导体装置中，将第一无机绝缘层，半导体元件层，第二无机绝缘层，有机绝缘层和第三无机绝缘层依次层叠在基板上。第二无机绝缘层在设置在半导体元件层中的开口部分与第一无机绝缘层接触。第三无机绝缘层在设置在有机绝缘层中的开口部分与第二无机绝缘层接触。在第二无机绝缘层和第三无机绝缘层相互接触的区域中，第二无机绝缘层具有多个不规则或开口。

5. 发明授权

US09006051B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09006051B2
公开(公告)日：2015-04-14
申请号：US12423563
申请日：2009-04-14
申请人： Yoshiaki Oikawa , Masayuki Kajiwara , Masataka Nakada , Masami Jintyou , Shunpei Yamazaki
发明人： Yoshiaki Oikawa , Masayuki Kajiwara , Masataka Nakada , Masami Jintyou , Shunpei Yamazaki
IPC分类号： H01L21/56 , H01L21/336 , H01L27/12 , H01L23/31
CPC分类号： H01L27/1266 , H01L21/568 , H01L23/3107 , H01L23/3114 , H01L27/1214 , H01L29/78606 , H01L29/78666 , H01L29/78669 , H01L2924/0002 , H01L2924/12044 , H01L2924/19041 , H01L2924/00
摘要： An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
摘要翻译：本发明的目的是通过降低膜的剥离度来提高半导体器件的耐水性和可靠性。在半导体装置中，将第一无机绝缘层，半导体元件层，第二无机绝缘层，有机绝缘层和第三无机绝缘层依次层叠在基板上。第二无机绝缘层在设置在半导体元件层中的开口部分与第一无机绝缘层接触。第三无机绝缘层在设置在有机绝缘层中的开口部分与第二无机绝缘层接触。在第二无机绝缘层和第三无机绝缘层相互接触的区域中，第二无机绝缘层具有多个不规则或开口。

6. 发明授权

US09929220B2 Light emitting device and electronic device 有权
公开(公告)号：US09929220B2
公开(公告)日：2018-03-27
申请号：US12651734
申请日：2010-01-04
申请人： Shunpei Yamazaki , Masahiro Katayama , Shingo Eguchi , Yoshiaki Oikawa , Ami Nakamura , Satoshi Seo , Kaoru Hatano
发明人： Shunpei Yamazaki , Masahiro Katayama , Shingo Eguchi , Yoshiaki Oikawa , Ami Nakamura , Satoshi Seo , Kaoru Hatano
IPC分类号： H01L27/32 , H05B33/02 , H05B33/04 , H05B33/12 , H01L27/12 , H01L29/786 , H01L51/00 , H01L51/52
CPC分类号： H01L27/3246 , H01L27/1214 , H01L27/1218 , H01L27/1266 , H01L29/7869 , H01L51/003 , H01L51/52 , H01L51/524 , H01L51/5253 , H01L2251/5338 , H05B33/02 , H05B33/04 , H05B33/12
摘要： Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are formed over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element formed over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof.

7. 发明授权

US09337244B2 Light-emitting device and electronic device using light-emitting device 有权
标题翻译：发光装置和使用发光装置的电子装置
公开(公告)号：US09337244B2
公开(公告)日：2016-05-10
申请号：US13404692
申请日：2012-02-24
申请人： Kaoru Hatano , Satoshi Seo , Akihiro Chida , Yoshiaki Oikawa
发明人： Kaoru Hatano , Satoshi Seo , Akihiro Chida , Yoshiaki Oikawa
IPC分类号： H01L33/08 , H01L27/32 , H01L51/52
CPC分类号： H01L27/3246 , H01L51/525
摘要： Provided is a highly reliable light-emitting device in which a light-emitting element is prevented from being damaged when external physical force is applied. The light-emitting device includes a light-emitting element formed over a first substrate, including a first electrode layer, a light-emitting layer, and a second electrode layer; a structure body formed over the first substrate; a second substrate provided to face the first substrate; and a bonding layer provided between the first substrate and the second substrate. The light-emitting layer is separated by the structure body. By strengthening adhesion between the structure body and the bonding layer, or between the structure body and the second electrode, the highly reliable light-emitting device in which damage of the light-emitting element is prevented can be provided.
摘要翻译：提供了一种高度可靠的发光装置，其中当施加外部物理力时防止发光元件被损坏。发光装置包括形成在第一基板上的发光元件，包括第一电极层，发光层和第二电极层; 形成在所述第一基板上的结构体; 设置成面对第一基板的第二基板; 以及设置在第一基板和第二基板之间的接合层。发光层被结构体分开。通过加强结构体与结合层之间或结构体与第二电极之间的粘附性，可以提供防止发光元件损坏的高度可靠的发光装置。

8. 发明授权

US09006729B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09006729B2
公开(公告)日：2015-04-14
申请号：US12943558
申请日：2010-11-10
申请人： Kengo Akimoto , Junichiro Sakata , Yoshiaki Oikawa , Shunpei Yamazaki
发明人： Kengo Akimoto , Junichiro Sakata , Yoshiaki Oikawa , Shunpei Yamazaki
IPC分类号： H01L29/10 , H01L29/12 , H01L29/786 , H01L29/45
CPC分类号： H01L29/7869 , H01L29/45
摘要： It is an object to provide a method for manufacturing a highly reliable semiconductor device having a thin film transistor formed using an oxide semiconductor and having stable electric characteristics. The semiconductor device includes an oxide semiconductor film overlapping with a gate electrode with a gate insulating film interposed therebetween; and a source electrode and a drain electrode which are in contact with the oxide semiconductor film. The source electrode and the drain electrode include a mixture, metal compound, or alloy containing one or more of a metal with a low electronegativity such as titanium, magnesium, yttrium, aluminum, tungsten, and molybdenum. The concentration of hydrogen in the source electrode and the drain electrode is 1.2 times, preferably 5 times or more as high as that of hydrogen in the oxide semiconductor film.
摘要翻译：本发明的目的是提供一种用于制造具有使用氧化物半导体形成并且具有稳定的电特性的薄膜晶体管的高度可靠的半导体器件的方法。半导体器件包括与栅电极重叠的氧化物半导体膜，其间插入有栅极绝缘膜; 以及与氧化物半导体膜接触的源电极和漏电极。源电极和漏极包括含有一种或多种具有低电负性的金属如钛，镁，钇，铝，钨和钼的混合物，金属化合物或合金。源电极和漏电极中的氢浓度是氧化物半导体膜中的氢的浓度的1.2倍，优选为5倍以上。

9. 发明授权

US08803298B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08803298B2
公开(公告)日：2014-08-12
申请号：US13354635
申请日：2012-01-20
申请人： Yoshiaki Oikawa , Shingo Eguchi
发明人： Yoshiaki Oikawa , Shingo Eguchi
IPC分类号： H01L23/02
CPC分类号： H01L23/60 , H01L23/3107 , H01L23/66 , H01L2223/6677 , H01L2924/0002 , H01L2924/12044 , H01L2924/3025 , H01L2924/00
摘要： With the use of a conductive shield formed on the top or bottom side of a semiconductor integrated circuit, an electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge is prevented, and sufficient communication capability is obtained. With the use of a pair of insulators which sandwiches the semiconductor integrated circuit, a highly reliable semiconductor device that is reduced in thickness and size and has resistance to an external stress can be provided. A semiconductor device can be manufactured with high yield while defects of shapes and characteristics due to an external stress or electrostatic discharge are prevented in the manufacturing process.
摘要翻译：通过使用形成在半导体集成电路的顶部或底部的导电屏蔽，防止由静电放电引起的半导体集成电路的静电击穿（电路的故障或半导体元件的损坏），并且充分的通信获得能力。通过使用夹持半导体集成电路的一对绝缘体，可以提供厚度和尺寸减小并且具有耐外部应力的高度可靠的半导体器件。可以以高产率制造半导体器件，同时在制造过程中防止由外部应力或静电放电引起的形状和特性的缺陷。

10. 发明授权

US08654272B2 Semiconductor device wherein each of a first oxide semiconductor layer and a second oxide semiconductor layer includes a portion that is in an oxygen-excess state which is in contact with a second insulatng layer 有权
标题翻译：半导体器件，其中第一氧化物半导体层和第二氧化物半导体层中的每一个包括处于与第二绝缘层接触的氧过剩状态的部分
公开(公告)号：US08654272B2
公开(公告)日：2014-02-18
申请号：US12848404
申请日：2010-08-02
申请人： Shunpei Yamazaki , Junichiro Sakata , Masayuki Sakakura , Yoshiaki Oikawa , Kenichi Okazaki , Hotaka Maruyama , Masashi Tsubuku
发明人： Shunpei Yamazaki , Junichiro Sakata , Masayuki Sakakura , Yoshiaki Oikawa , Kenichi Okazaki , Hotaka Maruyama , Masashi Tsubuku
IPC分类号： G02F1/136 , G02F1/1343
CPC分类号： H01L27/1225 , G02F1/13306 , G02F1/133345 , G02F1/133528 , G02F1/1337 , G02F1/1339 , G02F1/13394 , G02F1/134336 , G02F1/13439 , G02F1/13454 , G02F1/136204 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , G02F2001/133357 , G02F2201/123 , G11C19/28 , H01L27/124 , H01L27/1255 , H01L27/127 , H01L27/1288 , H01L29/247 , H01L29/78618 , H01L29/78648 , H01L29/78693 , H01L29/78696
摘要： An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.
摘要翻译：目的是提高半导体器件的可靠性。提供了包括驱动电路部分和在相同基板上的显示部分（也称为像素部分）的半导体器件。驱动器电路部分和显示部分包括其中半导体层包括氧化物半导体的薄膜晶体管; 第一布线和第二布线。薄膜晶体管各自包括源极电极层和漏极电极层。在驱动电路部分的薄膜晶体管中，半导体层夹在栅电极层和导电层之间。第一布线和第二布线在通过氧化物导电层设置在栅极绝缘膜中的开口中彼此电连接。

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