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1. 发明授权

US06466988B1 Multiprocessor synchronization and coherency control system 有权
标题翻译：多处理器同步和一致性控制系统
公开(公告)号：US06466988B1
公开(公告)日：2002-10-15
申请号：US09473276
申请日：1999-12-28
申请人： Naonobu Sukegawa , Kouki Uwano , Shigeko Hashimoto , Masakazu Fukagawa , Eiki Kamada
发明人： Naonobu Sukegawa , Kouki Uwano , Shigeko Hashimoto , Masakazu Fukagawa , Eiki Kamada
IPC分类号： G06F1300
CPC分类号： G06F12/0815 , G06F12/0822
摘要： A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.
摘要翻译：共享的主存储器型多处理器被布置成具有开关连接类型。多处理器准备用于输出同步事务的指令。当每个CPU执行该指令时，在输出上述指令的所有事务之后，将同步事务输出到主存储器和相干控制器。通过同步事务，主存储器将存储器访问序列化，并且相干控制器保证高速缓存一致性控制的完成。这使得可以同时序列化存储器访问并保证高速缓存一致性控制的完成。

2. 发明授权

US06263406B1 Parallel processor synchronization and coherency control method and system 失效
标题翻译：并行处理器同步和一致性控制方法及系统
公开(公告)号：US06263406B1
公开(公告)日：2001-07-17
申请号：US09153872
申请日：1998-09-16
申请人： Kohki Uwano , Shigeko Hashimoto , Naonobu Sukegawa , Tadaaki Isobe , Miki Miyaki , Tatsuya Ichiki
发明人： Kohki Uwano , Shigeko Hashimoto , Naonobu Sukegawa , Tadaaki Isobe , Miki Miyaki , Tatsuya Ichiki
IPC分类号： G06F1300
CPC分类号： G06F12/0815 , G06F9/52 , G06F9/522
摘要： Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.
摘要翻译：多处理器系统中的每个处理器具有用于在执行诸如开始，结束或屏障同步指令之类的同步指令时向连接到其的存储控制器（SC）发送同步信号的电路。每个SC具有电路，用于在检测到由地址管理表FAA进行的检查的完成以及发出对应于在之前发出的存储指令的必要的高速缓存取消请求之前通知对应的处理器建立同步同时指令以及所有处理器已经发送了其同步信号以及所有缓存取消请求的发出已经完成的事实。

3. 发明授权

US5978830A Multiple parallel-job scheduling method and apparatus 失效
标题翻译：多个并行作业调度方法和装置
公开(公告)号：US5978830A
公开(公告)日：1999-11-02
申请号：US28351
申请日：1998-02-24
申请人： Akihiro Nakaya , Takashi Nishikado , Hiroyuki Kumazaki , Naonobu Sukegawa , Kei Nakajima , Masakazu Fukagawa
发明人： Akihiro Nakaya , Takashi Nishikado , Hiroyuki Kumazaki , Naonobu Sukegawa , Kei Nakajima , Masakazu Fukagawa
IPC分类号： G06F15/80 , G06F9/45 , G06F9/48 , G06F9/50 , G06F9/00
CPC分类号： G06F9/52 , G06F8/456 , G06F8/457 , G06F8/458 , G06F9/5027 , G06F2209/503
摘要： Multiple parallel-job scheduling method and apparatus are provided which can improve the utilization of all processors in a system when a plurality of parallel jobs are executed concurrently. A plurality of processors constituting a computer system and each having the equal function are logically categorized into serial processors for executing a serial computing part or a parallel computing part of a parallel job and a parallel processor group consisting of multiple processors for executing the parallel computing part of the parallel job in parallel. In order that the parallel processors are shared by a plurality of parallel jobs, a synchronization range indicator is provided which can control by program whether the parallel processors are available in correspondence to the respective serial processors. In response to a request for using the parallel processors from a serial processor for which the parallel processors are so set as to be available by means of the synchronization range indicator, operation can be carried out without invoking an interrupt.
摘要翻译：提供了多个并行作业调度方法和装置，当同时执行多个并行作业时，可以提高系统中所有处理器的利用率。构成计算机系统并且具有相同功能的多个处理器被逻辑地分类为用于执行并行作业的串行计算部分或并行计算部分的串行处理器以及由多个处理器组成的并行处理器组，用于执行并行计算部分的并行作业并行。为了使并行处理器由多个并行作业共享，提供了同步范围指示符，其可以通过程序来控制并行处理器是否对应于各个串行处理器可用。响应于来自串行处理器的并行处理器的请求，并行处理器通过同步范围指示器将并行处理器设置为可用，可以在不调用中断的情况下执行操作。

4. 发明申请

US20080222434A1 Method of power-aware job management and computer system 有权
标题翻译：功率感知工作管理和计算机系统的方法
公开(公告)号：US20080222434A1
公开(公告)日：2008-09-11
申请号：US12068086
申请日：2008-02-01
申请人： Masaaki Shimizu , Naonobu Sukegawa
发明人： Masaaki Shimizu , Naonobu Sukegawa
IPC分类号： G06F9/46 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/329 , G06F9/5027 , Y02D10/22 , Y02D10/24
摘要： Provided is a method used in a computer system which includes at least one host computer, the method including managing a job to be executed by the host computer and a power supply of the host computer, the method including the procedures of: receiving the job; storing the received job; scheduling an execution plan for the stored job; determining, based on the execution plan of the job, a timing to execute power control of the host computer; determining a host computer to execute the power control when the determined timing to execute the power control is reached; controlling the power supply of the determined host computer; and executing the scheduled job.
摘要翻译：提供了一种在计算机系统中使用的方法，其包括至少一个主计算机，所述方法包括管理由主计算机执行的作业和主计算机的电源，所述方法包括以下过程：接收作业; 存储所接收的作业; 调度存储作业的执行计划; 基于作业的执行计划确定执行主计算机的功率控制的定时; 当达到确定的执行功率控制的定时时，确定主计算机执行功率控制; 控制所确定的主机的电源; 并执行预定作业。

5. 发明授权

US07159079B2 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US07159079B2
公开(公告)日：2007-01-02
申请号：US10886036
申请日：2004-07-08
申请人： Naonobu Sukegawa
发明人： Naonobu Sukegawa
IPC分类号： G06F13/00
CPC分类号： G06F12/0817 , G06F12/0813 , G06F12/0831
摘要： A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for storing bus-splitting information are provided in a directory control circuit 150 that controls cache invalidation. The bus is dynamically set to a split or connected state to fit a particular execution form of a job, and the directory control circuit uses the directory in order to manage all inter-CPU coherence control sequences in response to the above setting, while at the same time, in accordance with information of the group setup register, omitting dynamically bus-connected CPU-to-CPU cache coherence control, and conducting only bus-split CPU-to-CPU cache coherence control through the network.Thus, decreases in performance scalability due to an inter-CPU coherence-processing overhead are relieved in a system having multiple CPUs and guaranteeing inter-CPU cache coherence by use of hardware.
摘要翻译：在CPU之间提供可拆卸/可连接总线140和用于在CPU之间传输相干事务的网络1000，并且在目录控制电路150中提供用于存储总线分解信息的目录160和组设置寄存器170，其控制高速缓存无效。总线被动态设置为分割或连接状态以适合作业的特定执行形式，并且目录控制电路使用该目录以便响应于上述设置来管理所有CPU间相干控制序列，而在同时，根据组设置寄存器的信息，省略动态总线连接的CPU到CPU缓存一致性控制，并通过网络进行总线分割CPU到CPU缓存一致性控制。因此，在具有多个CPU的系统中减轻了由于CPU间相干处理开销引起的性能可扩展性的降低，并且通过使用硬件来保证CPU间高速缓存的一致性。

6. 发明授权

US06295579B1 Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas 失效
标题翻译：并行处理器系统包括具有可独立寻址的本地和远程数据区的高速缓存存储器子系统
公开(公告)号：US06295579B1
公开(公告)日：2001-09-25
申请号：US09070851
申请日：1998-05-01
申请人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
发明人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0848 , G06F2212/272
摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.
摘要翻译：并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

7. 发明申请

US20080059715A1 Computer system and control method for controlling processor 有权
标题翻译：用于控制处理器的计算机系统和控制方法
公开(公告)号：US20080059715A1
公开(公告)日：2008-03-06
申请号：US11705410
申请日：2007-02-13
申请人： Aki Tomita , Naonobu Sukegawa
发明人： Aki Tomita , Naonobu Sukegawa
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor reads a program including a prefetch command and a load command and data from a main memory, and executes the program. The processor includes: a processor core that executes the program; a L2 cache that stores data on the main memory for each predetermined unit of data storage; and a prefetch unit that pre-reads the data into the L2 cache from the main memory on the basis of a request for prefetch from the processor core. The prefetch unit includes: a L2 cache management table including an area in which a storage state is held for each position in the unit of data storage of the L2 cache and an area in which a request for prefetch is reserved; and a prefetch control unit that instructs, the L2 cache to perform the request for prefetch reserved or the request for prefetch from the processor core.
摘要翻译：处理器从主存储器读取包括预取命令和加载命令以及数据的程序，并执行该程序。处理器包括：执行程序的处理器核心; L2缓存，用于在每个预定的数据存储单元上存储主存储器上的数据; 以及预取单元，其基于来自处理器核的预取请求，从主存储器预读取数据到L2高速缓存中。预取单元包括：L2高速缓存管理表，其包括以L2缓存的数据存储为单位的每个位置保持存储状态的区域以及保留预取请求的区域; 以及预取控制单元，其指示L2高速缓存从所述处理器核心执行预取请求或预取请求。

8. 发明申请

US20070124523A1 Heterogeneous multiprocessor system and OS configuration method thereof 有权
标题翻译：异构多处理器系统及其OS配置方法
公开(公告)号：US20070124523A1
公开(公告)日：2007-05-31
申请号：US11357088
申请日：2006-02-21
申请人： Masaaki Shimizu , Naonobu Sukegawa
发明人： Masaaki Shimizu , Naonobu Sukegawa
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt in each CPU; means which inquires the accepted interrupt of an interrupt destination management table to select an interrupt destination CPU; means which queues the accepted interrupt; means which generates an inter-CPU interrupt to the selected interrupt destination CPU; each means which receives the inter-CPU interrupt in the interrupt source CPU, performs interrupt process of the interrupt source CPU, and generates the inter-CPU interrupt to the interrupt source CPU in the interrupt destination CPU; means which performs an interrupt end process; and means which performs interrupt process in its own CPU when the interrupt destination CPU selected as a result of the inquiry to the interrupt destination management table is its own CPU.
摘要翻译：在用于算术运算的处理器中产生的中断处理被卸载到系统控制处理器上，从而减少对处理器的干扰以进行算术运算。异构多处理器系统包括：在每个CPU中接受中断的装置; 查询中断目的地管理表的接受中断以选择中断目的地CPU的装置; 意味着对接受的中断进行排队; 为所选择的中断目标CPU产生CPU间中断的装置; 在中断源CPU中接收到CPU间中断的各种方式，执行中断源CPU的中断处理，并在中断目标CPU中产生中断源CPU中断CPU中断; 执行中断结束过程的手段; 以及当作为对中断目的地管理表的查询结果而选择的中断目的地CPU是其自己的CPU时，在其自己的CPU中执行中断处理的装置。

9. 发明授权

US06335903B2 Memory system 失效
标题翻译：内存系统
公开(公告)号：US06335903B2
公开(公告)日：2002-01-01
申请号：US09778785
申请日：2001-02-08
申请人： Tetsuhito Nakamura , Naonobu Sukegawa , Tsuguo Matsuura , Masanao Ito
发明人： Tetsuhito Nakamura , Naonobu Sukegawa , Tsuguo Matsuura , Masanao Ito
IPC分类号： G11C800
CPC分类号： G06F13/1631 , G06F12/0215
摘要： A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.
摘要翻译：具有DRAM或同步DRAM作为存储单元的存储器系统。存储器控制器，其与从存储器访问请求生成器接收的存储器访问请求相对应地控制存储器单元，具有用于存储从发布的存储器访问请求中提取的行地址的行地址缓冲器，避免将相同行地址注册到不同的位置用于存储指向存储行地址的行地址缓冲器中的注册条目的指针寄存器，对应检测电路，通过比较存储的指针来检测发出的访问请求的行地址是否相互对应;存储器单元控制电路，其连续地向DRAM发送具有彼此对应的行地址的多个请求的列地址。

10. 发明授权

US5978894A Method of interprocessor data transfer using a network, virtual addresses and paging, a buffer, flags, data transfer status information and user accessible storage areas in main memory 失效
标题翻译：使用网络的处理器间数据传输方法，虚拟地址和寻呼，缓冲区，标志，数据传输状态信息和主存储器中用户可访问的存储区域
公开(公告)号：US5978894A
公开(公告)日：1999-11-02
申请号：US757997
申请日：1996-11-27
申请人： Naonobu Sukegawa , Masanao Ito , Yoshiko Tamaki
发明人： Naonobu Sukegawa , Masanao Ito , Yoshiko Tamaki
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , Y10S707/99953 , Y10S707/99955
摘要： To realize interprocessor data transfer with the data receive area not fixed in the real memory and with less overhead for synchronization, the send node sends to the destination node, data, a virtual address of a receive area, an address of a receive control flag, a comparison value, and a comparison method. Network adaptor in the destination node judges whether the transfer condition is fulfilled, based on the comparison value, the comparison method and the semaphore in the receive control flag designated by the receive control flag address. Network adaptor further detects whether the receive area of the virtual address is in the main storage, based on the virtual address and the address translation table. The send data is stored in the receive buffer provided in the area for OS, when the above-mentioned condition is not fulfilled or the receive area is not in the main storage. Either when the destination node program issues a specific system call or when the program issues a reading instruction to the data in the receive area and a page fault is generated, OS moves the send data from the receive buffer to the receive area.
摘要翻译：为了实现与实际存储器中不固定的数据接收区域的处理器间数据传输，并且具有较少的同步开销，发送节点向目的地节点发送数据，接收区域的虚拟地址，接收控制标志的地址，比较值和比较方法。目的地节点中的网络适配器根据由接收控制标志地址指定的接收控制标志中的比较值，比较方法和信号量来判断传送条件是否被满足。网络适配器还基于虚拟地址和地址转换表来检测虚拟地址的接收区域是否在主存储器中。当不满足上述条件或接收区域不在主存储器中时，发送数据被存储在用于OS的区域中的接收缓冲器中。当目的地节点程序发出特定的系统调用时，或者当程序向接收区域中的数据发出读取指令并产生页面错误时，OS将发送数据从接收缓冲器移动到接收区域。

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