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1. 发明授权

US5845321A Store buffer apparatus with two store buffers to increase throughput of a store operation 失效
标题翻译：具有两个存储缓冲器的存储缓冲装置，以增加存储操作的吞吐量
公开(公告)号：US5845321A
公开(公告)日：1998-12-01
申请号：US729837
申请日：1996-10-15
申请人： Motohisa Ito , Eiki Kamada , Toshiko Isobe , Kei Yamamoto , Katsutoshi Uehara
发明人： Motohisa Ito , Eiki Kamada , Toshiko Isobe , Kei Yamamoto , Katsutoshi Uehara
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0855
摘要： A store buffer apparatus connected to a CPU and a main storage unit includes a first buffer for holding a pair of store address and store data in the main storage unit supplied from an operation execution unit of the CPU, a first latch connected to the first buffer means for holding the store address, a second latch connected to the first latch for holding an output of the first latch, a judgment device for comparing an output read out from the address array with an output of the second latch to thereby judge whether the cache hit check for the store address is successful or not and a second buffer for holding the pair of store data and store address having successful cache hit check judged by the judgment device. Occurrence of the state that the store buffer is full is reduced. Two data stored in the second buffer can possess a format into which the two data can be merged.
摘要翻译：连接到CPU和主存储单元的存储缓冲装置包括：第一缓冲器，用于保持一对存储地址并将数据存储在从CPU的操作执行单元提供的主存储单元中;第一锁存器，连接到第一缓冲器用于保存存储地址的装置，连接到第一锁存器的第二锁存器，用于保持第一锁存器的输出;判断装置，用于将从地址阵列读出的输出与第二锁存器的输出进行比较，从而判断高速缓存命中检查存储地址是否成功，以及第二缓冲器，用于保持由判断装置判断的具有成功的高速缓存命中检查的一对存储数据和存储地址。存储缓冲区已满的状态的发生被减少。存储在第二缓冲器中的两个数据可以具有可以合并两个数据的格式。

2. 发明授权

US5075849A Information processor providing enhanced handling of address-conflicting instructions during pipeline processing 失效
标题翻译：信息处理者在管道加工期间提供地址冲突指令的增强处理
公开(公告)号：US5075849A
公开(公告)日：1991-12-24
申请号：US292346
申请日：1988-12-30
申请人： Kazunori Kuriyama , Yooichi Shintani , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Kazunori Kuriyama , Yooichi Shintani , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3824
摘要： An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction. Then, before the one address data is updated by the preceding instruction after the first operand has been fetched from the main memory in an operand fetch stage for the preceding instruction, an operation determined by the preceding instruction is performed on the output of the address adder and the fetched first operand to generate an address equal to a sum of the plurality of address data, excluding said one address, and the execution result data for the preceding instruction, and this address is used as the address of the second operand of the succeeding instruction.
摘要翻译：信息处理器通过确定执行中的前一指令是否从主存储器取出第一操作数，检测基于第一操作数的执行结果数据，并更新由a至执行后续指令，执行结果数据。当检测到冲突时，由地址加法器提供由前一条指令的类型确定的多个地址数据中的至少一些，以完成后续指令的操作数地址计算阶段。然后，在前一条指令的操作数获取级中从主存储器取出第一操作数之前，先前指令更新一个地址数据之前，对地址加法器的输出执行由先前指令确定的操作以及所取出的第一操作数，以产生等于除所述一个地址之外的多个地址数据之和的地址和前一条指令的执行结果数据，并且该地址被用作后续的第二操作数的地址指令。

3. 发明授权

US4760520A Data processor capable of executing instructions under prediction 失效
标题翻译：能够执行预测指令的数据处理器
公开(公告)号：US4760520A
公开(公告)日：1988-07-26
申请号：US793545
申请日：1985-10-31
申请人： Yooichi Shintani , Tohru Shonai , Eiki Kamada , Shigeo Takeuchi
发明人： Yooichi Shintani , Tohru Shonai , Eiki Kamada , Shigeo Takeuchi
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3889 , G06F9/3842
摘要： A buffer or a plurality of buffers are provided each for holding a write address and an address specifying a write position which are obtained as a result of an execution based on a predicted result. The execution of the instruction is continued up to the operation stage regadless of whether or not the instruction is being executed in the predicted state, the data and the write address are held in the buffer written. The data in the buffer is canceled if the prediction is found to be wrong when the predicted state is completed, and the data is utilized if the prediction is found to be correct.
摘要翻译：提供缓冲器或多个缓冲器，每个缓冲器用于保持写入地址和指定作为基于预测结果的执行结果而获得的写入位置的地址。指令的执行继续到操作阶段，无论在预测状态下是否执行指令，数据和写入地址都被保存在写入的缓冲器中。如果在预测状态完成时发现预测错误，则缓冲器中的数据被取消，并且如果发现该预测是正确的，则利用该数据。

4. 发明授权

US06466988B1 Multiprocessor synchronization and coherency control system 有权
标题翻译：多处理器同步和一致性控制系统
公开(公告)号：US06466988B1
公开(公告)日：2002-10-15
申请号：US09473276
申请日：1999-12-28
申请人： Naonobu Sukegawa , Kouki Uwano , Shigeko Hashimoto , Masakazu Fukagawa , Eiki Kamada
发明人： Naonobu Sukegawa , Kouki Uwano , Shigeko Hashimoto , Masakazu Fukagawa , Eiki Kamada
IPC分类号： G06F1300
CPC分类号： G06F12/0815 , G06F12/0822
摘要： A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.
摘要翻译：共享的主存储器型多处理器被布置成具有开关连接类型。多处理器准备用于输出同步事务的指令。当每个CPU执行该指令时，在输出上述指令的所有事务之后，将同步事务输出到主存储器和相干控制器。通过同步事务，主存储器将存储器访问序列化，并且相干控制器保证高速缓存一致性控制的完成。这使得可以同时序列化存储器访问并保证高速缓存一致性控制的完成。

5. 发明授权

US5931895A Floating-point arithmetic processing apparatus 失效
标题翻译：浮点算术处理装置
公开(公告)号：US5931895A
公开(公告)日：1999-08-03
申请号：US789430
申请日：1997-01-29
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Noriyasu Ido , Yoshikazu Kiyoshige , Takahiro Nishiyama , Eiki Kamada
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Noriyasu Ido , Yoshikazu Kiyoshige , Takahiro Nishiyama , Eiki Kamada
IPC分类号： G06F7/38 , G06F5/01 , G06F7/00 , G06F7/483 , G06F7/74 , G06F7/76 , G06F7/52
CPC分类号： G06F5/012 , G06F7/483
摘要： A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.
摘要翻译：一种浮点运算处理装置，具有通过从中间结果的指数的值减去归一化数的最小值的指数来生成用于归一化偏移的极限值的电路，以及生成作为归一化的归一化的电路移位数，使中间结果的尾数所需的移位数中的较小的一个是归一化数，以及归一化移位的极限值。浮点运算处理装置还具有电路，该电路具有用于检测在舍入处理之前的溢出条件的电路和用于在溢出的情况下产生值的电路，从而仅当预定值仅在在舍入处理之前检测到溢出条件，但是在另一种情况下，通过执行归一化处理和舍入处理获得的结果被传送。在四舍五入处理之前没有发生溢出，而在舍入处理后发生溢出的情况下，通过执行归一化处理和舍入处理获得的结果作为最终结果被传递。

6. 发明授权

US5922068A Information processing system and information processing method for executing instructions in parallel 失效
标题翻译：用于并行执行指令的信息处理系统和信息处理方法
公开(公告)号：US5922068A
公开(公告)日：1999-07-13
申请号：US888645
申请日：1997-07-07
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

7. 发明授权

US5742782A Processing apparatus for executing a plurality of VLIW threads in parallel 失效
标题翻译：并行执行多个VLIW线程的处理装置
公开(公告)号：US5742782A
公开(公告)日：1998-04-21
申请号：US422220
申请日：1995-04-14
申请人： Motohisa Ito , Eiki Kamada
发明人： Motohisa Ito , Eiki Kamada
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/3851 , G06F9/3853
摘要： An information processing apparatus based on a VLIW system which eliminates an idle execution part generated during execution and which uses execution parts efficiently to obtain a high parallel processing ability of instruction execution. The information processing apparatus simultaneously executes m of multiple threads of long instructions each made up of n of operational instructions. When it is desired to process 3 threads with 4 of the operational instructions as an example, the information processing apparatus includes 3 instruction decoders corresponding to the 3 threads, 4 instruction schedulers for the operational instructions, and 4 execution parts corresponding to the 4 operational instructions. The instruction decoders, which are operated independently of each other, include a circuit for resolving a resource competition relationship and a data dependent relationship and a circuit for controlling instruction issuance. Thus, even when a previous instruction is being executed, the subsequent instructions are issued to the respective instruction schedulers respectively independently when there is no resource competition relation and also no data dependent relationship. Each of the instruction schedulers performs scheduling operation over the operational instructions to be sent to the corresponding execution parts between the plurality of threads.
摘要翻译：一种基于VLIW系统的信息处理装置，其消除了在执行期间产生的空闲执行部分并且有效地使用执行部分以获得指令执行的高并行处理能力。信息处理装置同时执行由n个操作指令构成的多个指令的多个线程的m个。当希望用4个操作指令处理3个线程作为示例时，信息处理设备包括对应于3个线程的3个指令解码器，用于操作指令的4个指令调度器，以及与4个操作指令相对应的4个执行部分。指令解码器彼此独立地操作，包括用于解决资源竞争关系和数据相关关系的电路以及用于控制指令发布的电路。因此，即使当前一个指令正在执行时，当没有资源竞争关系并且也没有与数据相关的关系时，随后的指令分别独立地被发布到各个指令调度器。每个指令调度器对要发送到多个线程之间的相应执行部分的操作指令执行调度操作。

8. 发明授权

US5600819A Memory with sequential data transfer scheme 失效
标题翻译：具有顺序数据传输方案的存储器
公开(公告)号：US5600819A
公开(公告)日：1997-02-04
申请号：US207744
申请日：1994-03-09
申请人： Eiki Kamada , Satoshi Oguni
发明人： Eiki Kamada , Satoshi Oguni
IPC分类号： G06F13/16 , G06F12/00 , G06F12/06 , G11C7/10
CPC分类号： G11C7/1039
摘要： A memory array area of a semiconductor chip is divided into a plurality of partial memories. Each partial memory is provided with a register. The distance between adjacent registers is set shorter than a maximum distance which that data can travel in the memory in one data transfer cycle defined by a clock signal. These registers are serially connected and provides a path through which addresses, input data, and control signals are transferred to desired partial memories in synchronism with the clock signal. Output data and status signals are also transferred through these registers to a memory output terminal in synchronism with the clock signal.
摘要翻译：半导体芯片的存储器阵列区域被分成多个部分存储器。每个部分存储器都配有一个寄存器。相邻寄存器之间的距离设定为短于该数据可以在由时钟信号定义的一个数据传输周期内在存储器中行进的最大距离。这些寄存器被串行连接，并且提供了与时钟信号同步地址，输入数据和控制信号被传送到期望的部分存储器的路径。输出数据和状态信号也通过这些寄存器与时钟信号同步传送到存储器输出端。

9. 发明授权

US4928226A Data processor for parallelly executing conflicting instructions 失效
标题翻译：用于并行执行冲突指令的数据处理器
公开(公告)号：US4928226A
公开(公告)日：1990-05-22
申请号：US124839
申请日：1987-11-24
申请人： Eiki Kamada , Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Kiyoshi Inoue
发明人： Eiki Kamada , Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3836
摘要： A data processor includes an instruction detection unit for detecting that a succeeding instruction writes a read-out operand into a general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by an instruction hold unit; a conflict detection unit for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.
摘要翻译：数据处理器包括：指令检测单元，用于根据由指令保持单元提供的指令解码信息，检测后续指令将读出操作数写入通用寄存器组，而不对其进行算术或逻辑运算; 冲突检测单元，用于检测前一指令对通用寄存器组的通用寄存器执行写入操作的冲突状态，并且后续指令根据由指令保持提供的指令解码信息从同一通用寄存器读取操作数单元; 以及竞争检测单元，用于根据由指令保持单元提供的指令解码信息，检测前一指令对同一通用寄存器执行写操作的竞争状态，并且后续指令也对同一通用寄存器执行写操作。

10. 发明授权

US4858105A Pipelined data processor capable of decoding and executing plural instructions in parallel 失效
标题翻译：能够并行地解码和执行多个指令的流水线数据处理器
公开(公告)号：US4858105A
公开(公告)日：1989-08-15
申请号：US30434
申请日：1987-03-26
申请人： Kazunori Kuriyama , Yooichi Shintani , Akira Yamaoka , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Kazunori Kuriyama , Yooichi Shintani , Akira Yamaoka , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/3822 , G06F9/3836 , G06F9/3889
摘要： A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.
摘要翻译：流水线数据处理器包括用于在一对指令寄存器中存储两个指令的电路，用于检测这些指令是否是请求使用操作单元的指令与请求使用另一资源的指令的组合的电路，以及电路，用于当检测电路的判定为肯定时控制指令的执行，使得这些指令由操作单元和资源在多个级中执行。

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