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1. 发明申请

US20050281113A1 Data processing system and data processing method 审中-公开
标题翻译：数据处理系统和数据处理方法
公开(公告)号：US20050281113A1
公开(公告)日：2005-12-22
申请号：US11200104
申请日：2005-08-10
申请人： Naoki Yada , Eiichi Ishikawa , Mitsuru Hiraki , Shoji Shukuri
发明人： Naoki Yada , Eiichi Ishikawa , Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G06F12/16 , G06F11/10 , G06F15/78 , G11C7/00 , G11C16/06 , G11C29/00
CPC分类号： G06F11/1068
摘要： A data processing system (1) has an erasable and programmable non-volatile memory (5) and a central processing unit (2). The central processing unit allows only a specified partial storage area (20Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can b avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.
摘要翻译：数据处理系统（1）具有可擦除和可编程的非易失性存储器（5）和中央处理单元（2）。中央处理单元仅允许非易失性存储器的指定的部分存储区域（20Ba）用于软件ECC处理。由于将ECC代码单独添加到部分存储区域并且对其进行错误校正，从而增加重写保证的数量，所以与ECC代码的配置相比，可以避免基于ECC代码的每个存储区域的基本上不必要的浪费被添加到所有写入数据，而不管存储区域如何。此外，由于软件处理ECC处理，可以容易地选择与非易失性存储器的设备特性相匹配的ECC校正能力。

2. 发明授权

US06941505B2 Data processing system and data processing method 失效
标题翻译：数据处理系统和数据处理方法
公开(公告)号：US06941505B2
公开(公告)日：2005-09-06
申请号：US09938629
申请日：2001-08-27
申请人： Naoki Yada , Eiichi Ishikawa , Mitsuru Hiraki , Shoji Shukuri
发明人： Naoki Yada , Eiichi Ishikawa , Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G06F12/16 , G06F11/10 , G06F15/78 , G11C7/00 , G11C16/06 , G11C29/00
CPC分类号： G06F11/1068
摘要： A data processing system (1) has an erasable and programmable non-volatile memory (5) and a central processing unit (2). The central processing unit allows only a specified partial storage area (20Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can be avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.
摘要翻译：数据处理系统（1）具有可擦除和可编程的非易失性存储器（5）和中央处理单元（2）。中央处理单元仅允许非易失性存储器的指定的部分存储区域（20Ba）用于软件ECC处理。由于ECC代码被单独添加到部分存储区域并且对其进行错误校正，从而增加重写保证的数量，所以与ECC代码的配置相比，可以避免通过ECC代码对每个存储区域的基本上不必要的浪费被添加到所有写入数据，而不管存储区域如何。此外，由于软件处理ECC处理，可以容易地选择与非易失性存储器的设备特性相匹配的ECC校正能力。

3. 发明授权

US06873555B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrate circuit device 失效
标题翻译：半导体集成电路器件，存储器模块，存储器件和半导体集成电路器件的修复方法
公开(公告)号：US06873555B2
公开(公告)日：2005-03-29
申请号：US10912110
申请日：2004-08-06
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.
摘要翻译：为了提高修复LSI的缺陷的效率，提供了一种半导体集成电路装置，其包括中央处理单元，电可重新编程的非易失性存储器和易失性存储器，共享数据总线，其利用非易失性存储器的存储信息修复易失性存储器的缺陷。易失性存储器包括用于通过冗余存储单元来锁定用于修复有缺陷的正常存储单元的修复信息的易失性存储电路。非易失性存储器响应于指令初始化从其自身读出修复信息，并且易失性存储电路锁存修复信息。检测维修不需要保险丝编程电路，可以对修复后的故障进行新修复，即使在包装后也能修复新的缺陷。

4. 发明申请

US20050007857A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, MEMORY MODULE, STORAGE DEVICE AND THE METHOD FOR REPAIRING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路器件，存储器模块，存储器件及其修复半导体集成电路器件的方法
公开(公告)号：US20050007857A1
公开(公告)日：2005-01-13
申请号：US10912110
申请日：2004-08-06
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.
摘要翻译：为了提高修复LSI的缺陷的效率，提供了一种半导体集成电路装置，其包括中央处理单元，电可重新编程的非易失性存储器和易失性存储器，共享数据总线，其利用非易失性存储器的存储信息修复易失性存储器的缺陷。易失性存储器包括用于通过冗余存储单元来锁定用于修复有缺陷的正常存储单元的修复信息的易失性存储电路。非易失性存储器响应于指令初始化从其自身读出修复信息，并且易失性存储电路锁存修复信息。检测维修不需要保险丝编程电路，可以对修复后的故障进行新修复，即使在包装后也能修复新的缺陷。

5. 发明授权

US06449197B1 Semiconductor integrated circuit device, memory module, storage device 有权
标题翻译：半导体集成电路器件，存储器模块，存储器件
公开(公告)号：US06449197B1
公开(公告)日：2002-09-10
申请号：US09989133
申请日：2001-11-21
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C1604
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of a large-scale integrated circuit. A semiconductor integrated circuit device comprises, a central processing unit (10), an electrically reprogrammable nonvolatile memory (11) and a volatile memory (12, 13) while sharing a dat bus (16), and utilizes the stored information of the nonvolatile memory so as to repair a defect of the volatile memory. This volatile memory includes volatile storage circuit (12AR, 13AR) for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. Any fuse program circuit is not needed for the detect repair, but a defect to occur after a burn-in can be newly repaired so that the new defect can be repaired even after the packaging over a circuit substrate.
摘要翻译：一种半导体集成电路装置，包括中央处理单元（10），电可再编程非易失性存储器（11）和易失性存储器（12,13），同时共享数据总线（16），并且利用所存储的非易失性存储器的信息来修复易失性存储器的缺陷。这种易失性存储器包括易失性存储电路（12AR，13AR），用于通过冗余存储单元锁存用于修复有缺陷的正常存储单元的修复信息。非易失性存储器响应于初始化半导体集成电路器件的指令从其自身读出修复信息。响应于初始化指令，易失性存储电路锁存来自非易失性存储器的修复信息。任何保险丝编程电路不需要用于检测修复，但是可以重新修复在老化之后发生的缺陷，使得即使在电路基板上的封装之后也可以修复新的缺陷。

6. 发明授权

US06781893B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrate circuit device 失效
标题翻译：半导体集成电路器件，存储器模块，存储器件和半导体集成电路器件的修复方法
公开(公告)号：US06781893B2
公开(公告)日：2004-08-24
申请号：US10684414
申请日：2003-10-15
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C700
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.
摘要翻译：为了提高修复LSI的缺陷的效率，提供了一种半导体集成电路装置，其包括中央处理单元，电可重新编程的非易失性存储器和易失性存储器，共享数据总线，其利用非易失性存储器的存储信息修复易失性存储器的缺陷。易失性存储器包括用于通过冗余存储单元来锁定用于修复有缺陷的正常存储单元的修复信息的易失性存储电路。非易失性存储器响应于指令初始化从其自身读出修复信息，并且易失性存储电路锁存修复信息。检测维修不需要保险丝编程电路，可以对修复后的故障进行新修复，即使在包装后也能修复新的缺陷。

7. 发明授权

US06661712B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device 有权
公开(公告)号：US06661712B2
公开(公告)日：2003-12-09
申请号：US10379545
申请日：2003-03-06
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C1604
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

8. 发明授权

US06438029B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件，存储器模块，存储器件和半导体集成电路器件修复方法
公开(公告)号：US06438029B2
公开(公告)日：2002-08-20
申请号：US09756747
申请日：2001-01-10
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C1606
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of a large-scale integrated circuit. A semiconductor integrated circuit device comprises, a central processing unit (10), an electrically reprogrammable nonvolatile memory (11) and a volatile memory (12, 13) while sharing a dat bus (16), and utilizes the stored information of the nonvolatile memory so as to repair a defect of the volatile memory. This volatile memory includes volatile storage circuit (12AR, 13AR) for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. Any fuse program circuit is not needed for the detect repair, but a defect to occur after a burn-in can be newly repaired so that the new defect can be repaired even after the packaging over a circuit substrate.
摘要翻译：提高修复大型集成电路缺陷的效率。半导体集成电路装置包括：中央处理单元（10），电可重新编程的非易失性存储器（11）和易失性存储器（12,13），同时共享数据总线（16），并利用所存储的非易失性存储器的信息以便修复易失性存储器的缺陷。这种易失性存储器包括易失性存储电路（12AR，13AR），用于通过冗余存储单元锁存用于修复有缺陷的正常存储单元的修复信息。非易失性存储器响应于初始化半导体集成电路器件的指令从其自身读出修复信息。响应于初始化指令，易失性存储电路锁存来自非易失性存储器的修复信息。任何保险丝编程电路不需要用于检测修复，但是可以重新修复在老化之后发生的缺陷，使得即使在电路基板上的封装之后也可以修复新的缺陷。

9. 发明授权

US07031217B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件，存储器模块，存储器件和半导体集成电路器件修复方法
公开(公告)号：US07031217B2
公开(公告)日：2006-04-18
申请号：US11239372
申请日：2005-09-30
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LS1, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.
摘要翻译：为了提高修复LS1的缺陷的效率，提供了一种半导体集成电路装置，其包括中央处理单元，电可重新编程的非易失性存储器和易失性存储器，共享数据总线，其利用非易失性存储器的存储信息修复易失性存储器的缺陷。易失性存储器包括用于通过冗余存储单元来锁定用于修复有缺陷的正常存储单元的修复信息的易失性存储电路。非易失性存储器响应于指令初始化从其自身读出修复信息，并且易失性存储电路锁存修复信息。检测维修不需要保险丝编程电路，可以对修复后的故障进行新修复，即使在包装后也能修复新的缺陷。

10. 发明申请

US20050162961A1 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device 失效
公开(公告)号：US20050162961A1
公开(公告)日：2005-07-28
申请号：US11046769
申请日：2005-02-01
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C16/06 , G11C7/00 , G11C29/00
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

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