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1. 发明授权

US08299836B2 Level shift circuit and power conversion unit 有权
标题翻译：电平移位电路和电源转换单元
公开(公告)号：US08299836B2
公开(公告)日：2012-10-30
申请号：US13029341
申请日：2011-02-17
申请人： Naoki Sakurai , Junichi Sakano , Seigoh Yukutake
发明人： Naoki Sakurai , Junichi Sakano , Seigoh Yukutake
IPC分类号： H03L5/00
CPC分类号： H03K19/0175
摘要： In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.
摘要翻译：在电平移位电路中，当高电压侧的电源电压变化dV / dt发生并影响电路的逻辑电平时，在第一和第二逻辑电路中屏蔽并防止故障信号的通过通过利用在设定侧和复位侧出现这种变化的事实，通过来自时间常数生成电路的信号或者预先发生电力电压变化的部分。当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了错误的信号被发送到触发器，并且控制信号从低电压侧电路即使在半导体工艺中的每个元件存在生产变化时，也不会对高压侧电路产生故障。

2. 发明申请

US20110227626A1 LEVEL SHIFT CIRCUIT AND POWER CONVERSION UNIT 有权
标题翻译：电平转换电路和电源转换单元
公开(公告)号：US20110227626A1
公开(公告)日：2011-09-22
申请号：US13029341
申请日：2011-02-17
申请人： Naoki SAKURAI , Junichi Sakano , Seigoh Yukutake
发明人： Naoki SAKURAI , Junichi Sakano , Seigoh Yukutake
IPC分类号： H03L5/00
CPC分类号： H03K19/0175
摘要： In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.
摘要翻译：在电平移位电路中，当高电压侧的电源电压变化dV / dt发生并影响电路的逻辑电平时，在第一和第二逻辑电路中屏蔽并防止故障信号的通过通过利用在设定侧和复位侧出现这种变化的事实，通过来自时间常数生成电路的信号或者预先发生电力电压变化的部分。当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了错误的信号被发送到触发器，并且控制信号从低电压侧电路即使在半导体工艺中的每个元件存在生产变化时，也不会对高压侧电路产生故障。

3. 发明授权

US07522692B2 Isolator and a modem device using the isolator 失效
标题翻译：隔离器和使用隔离器的调制解调器设备
公开(公告)号：US07522692B2
公开(公告)日：2009-04-21
申请号：US11714856
申请日：2007-03-07
申请人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
发明人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
IPC分类号： H04L23/00 , H04B1/38 , H01L29/00
CPC分类号： H04L25/0266 , H01L2924/0002 , H04L25/0268 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L27/0002 , H04M11/06 , H01L2924/00
摘要： A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.
摘要翻译：提供一种通信系统，包括收发机和应用控制器，用于通过收发信机发送和接收信号。绝缘和分离收发器和应用控制器的隔离器包括在基板上彼此绝缘的初级和次级侧电路和用于在初级侧和第二侧之间传递信号的电容绝缘装置，同时将初级侧电路与次级侧隔离电路。

4. 发明授权

US5045904A Semiconductor device including an improved trench arrangement 失效
标题翻译：包括改进的沟槽布置的半导体器件
公开(公告)号：US5045904A
公开(公告)日：1991-09-03
申请号：US286870
申请日：1988-12-20
申请人： Yutaka Kobayashi , Akihiro Tanba , Ryoichi Hori , Kyoichiro Asayama , Seigoh Yukutake , Hiroyuki Miyazawa , Kazumasa Yanagisawa , Goro Kitsukawa
发明人： Yutaka Kobayashi , Akihiro Tanba , Ryoichi Hori , Kyoichiro Asayama , Seigoh Yukutake , Hiroyuki Miyazawa , Kazumasa Yanagisawa , Goro Kitsukawa
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L29/94
CPC分类号： H01L29/945 , H01L27/10829
摘要： A small and reliable semiconductor device is provided in a substrate which has an isolation trench and a capacitor trench. The isolation trench isolates a bipolar transistor from other semiconductor devices, and the capacitor trench provides capacitance to a memory cell which is formed in the substrate. The interior of the device isolation trench is kept in a floating state with respect to the surrounding semiconductor regions by forming an insulating film over the inner surface of the trench. In the capacitor trench, insulating layers and resilient conductive layers are formed alternately to form capacitance between the opposing conductive layers.
摘要翻译：在具有隔离沟槽和电容器沟槽的衬底中提供小型且可靠的半导体器件。隔离沟槽将双极晶体管与其它半导体器件隔离，并且电容器沟槽为在衬底中形成的存储器单元提供电容。器件隔离沟槽的内部通过在沟槽的内表面上形成绝缘膜而相对于周围的半导体区域保持浮置状态。在电容器沟槽中，交替地形成绝缘层和弹性导电层，以在相对的导电层之间形成电容。

5. 发明授权

US06603807B1 Isolator and a modem device using the isolator 失效
标题翻译：隔离器和使用隔离器的调制解调器设备
公开(公告)号：US06603807B1
公开(公告)日：2003-08-05
申请号：US09259058
申请日：1999-02-26
申请人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
发明人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
IPC分类号： H01L2900
CPC分类号： H04L25/0266 , H01L2924/0002 , H04L25/0268 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L27/0002 , H04M11/06 , H01L2924/00
摘要： An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.
摘要翻译：隔离器通过在半导体衬底上形成使用层间绝缘膜的电容绝缘屏障来制成单片，以通过单片隔离器使调制解调器装置小型化。

6. 发明授权

US5761150A Synchronous memory with pipelined write operation 失效
标题翻译：具有流水线写入操作的同步存储器
公开(公告)号：US5761150A
公开(公告)日：1998-06-02
申请号：US651873
申请日：1996-05-21
申请人： Seigoh Yukutake , Kinya Mitsumoto , Takashi Akioka , Masahiro Iwamura , Noboru Akiyama
发明人： Seigoh Yukutake , Kinya Mitsumoto , Takashi Akioka , Masahiro Iwamura , Noboru Akiyama
IPC分类号： G11C11/413 , G06F12/00 , G11C7/10 , G11C8/06 , G11C11/401 , G11C11/407 , G11C11/418 , G11C8/00 , G11C7/00
CPC分类号： G11C8/06 , G11C11/418 , G11C7/1072 , G11C2207/2218
摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
摘要翻译：提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。

7. 发明授权

US5661693A Memory device for synchronously reading and writing data 失效
标题翻译：用于同步读取和写入数据的存储器件
公开(公告)号：US5661693A
公开(公告)日：1997-08-26
申请号：US562194
申请日：1995-11-22
申请人： Takashi Akioka , Noboru Akiyama , Masahiro Iwamura , Seigoh Yukutake
发明人： Takashi Akioka , Noboru Akiyama , Masahiro Iwamura , Seigoh Yukutake
IPC分类号： G11C11/407 , G11C7/06 , G11C7/10 , G11C11/413 , G11C11/416 , G11C7/00
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1051
摘要： A synchronous memory device is provided in which the cycle time is shorter than conventional memory devices. For example, by providing an output latch in a sense amplifier on a bit line, the time period from input of a clock signal to latching data in the output latch is shortened. In case of plural bit lines, a selector for selecting data in a plural output latch and a latch for latching a sense amplifier selection are provided.
摘要翻译：提供了一种同步存储器件，其中循环时间比常规存储器件短。例如，通过在位线上的读出放大器中设置输出锁存器，从输入锁存器中的时钟信号输入到锁存数据的时间段被缩短。在多位线的情况下，提供用于选择多个输出锁存器中的数据的选择器和用于锁存读出放大器选择的锁存器。

8. 发明授权

US07289553B2 Isolator and a modem device using the isolator 失效
公开(公告)号：US07289553B2
公开(公告)日：2007-10-30
申请号：US10377670
申请日：2003-03-04
申请人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
发明人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
IPC分类号： H04B1/38 , H01L29/00
CPC分类号： H04L25/0266 , H01L2924/0002 , H04L25/0268 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L27/0002 , H04M11/06 , H01L2924/00
摘要： A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

9. 发明授权

US5742551A Memory circuit improved in electrical characteristics 失效
标题翻译：存储器电路改善了电气特性
公开(公告)号：US5742551A
公开(公告)日：1998-04-21
申请号：US463851
申请日：1995-06-05
申请人： Seigoh Yukutake , Yutaka Kobayashi , Takashi Akioka , Masahiro Iwamura
发明人： Seigoh Yukutake , Yutaka Kobayashi , Takashi Akioka , Masahiro Iwamura
IPC分类号： H03F3/72 , H03K17/62 , G11C7/02
CPC分类号： H03F3/72 , H03K17/6264 , H03F2203/7203
摘要： A constant current source is connected in series to a current source circuit including a MOS transistor which is used as a current source for a differential output amplifier circuit, an emitter follower circuit or a source follower circuit used with a semiconductor integrated circuit. In a multiplex circuit, an input signal is inputted to each of base terminals of a plurality of bipolar transistors. When one input signal is selected, the bipolar transistor corresponding to the selected input signal is made to be operable with an input signal from a signal input terminal by a control circuit. The bipolar transistors corresponding to the non-selection input signals are turned OFF irrespective of potential levels of the individual input signals by current drawing circuits. There is also disclosed a semiconductor memory circuit having a plurality of memory cells, a memory cell selection scheme and a sense amplifier for amplifying data outputted from the selected memory cell, in which a constant current circuit is provided in series connection to the sense amplifier to enhance the performance characteristics of the memory circuit. Also, a plural memory array scheme is disclosed which employs multiplexing techniques connected to presense amplifier circuits of the respective memory arrays.
摘要翻译：恒流源串联连接到电流源电路，该电流源电路包括用作差分输出放大器电路的电流源的MOS晶体管，射极跟随器电路或与半导体集成电路一起使用的源极跟随器电路。在复用电路中，输入信号被输入到多个双极晶体管的每个基极端子。当选择一个输入信号时，与所选择的输入信号相对应的双极晶体管可以通过控制电路与来自信号输入端的输入信号一起工作。对应于非选择输入信号的双极晶体管截止，而与当前绘图电路的各个输入信号的电位电平无关。还公开了具有多个存储单元的半导体存储器电路，存储单元选择方案和用于放大从所选择的存储单元输出的数据的读出放大器，其中恒定电流电路与读出放大器串联连接，提高存储电路的性能特点。此外，公开了一种多重存储器阵列方案，其采用连接到相应存储器阵列的预放大器电路的复用技术。

10. 发明授权

US5638335A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5638335A
公开(公告)日：1997-06-10
申请号：US649166
申请日：1996-05-17
申请人： Noboru Akiyama , Seigoh Yukutake , Sadayuki Ohkuma , Akihiko Emori , Takashi Akioka , Shuichi Miyaoka , Shinji Nakazato , Kinya Mitsumoto
发明人： Noboru Akiyama , Seigoh Yukutake , Sadayuki Ohkuma , Akihiko Emori , Takashi Akioka , Shuichi Miyaoka , Shinji Nakazato , Kinya Mitsumoto
IPC分类号： G11C11/41 , G11C5/00 , G06F13/00
CPC分类号： G11C5/06 , G11C7/062 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096
摘要： A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.
摘要翻译：一种存储器件，包括具有多个位的存储器阵列，包括奇偶校验位，并且包括多个存储器块，以及位结构改变部分，用于改变存储器阵列的输入/输出位，其中存储器块的数量被规定为3的整数倍，并且多个存储块的输入/输出位是偶数。因此，可以改变具有奇偶校验位并且能够将输入/输出位改变为多个位结构的半导体存储器的位结构，同时保持存储器块的位结构并且不增加传播延迟时间。

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