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1. 发明授权

US5031097A Direct memory access controller 失效
标题翻译：直接内存访问控制器
公开(公告)号：US5031097A
公开(公告)日：1991-07-09
申请号：US398815
申请日：1989-08-25
申请人： Naoichi Kitakami , Yuichi Nakao , Hiroyuki Kondo , Hideharu Toyomoto , Koji Tsuchihashi
发明人： Naoichi Kitakami , Yuichi Nakao , Hiroyuki Kondo , Hideharu Toyomoto , Koji Tsuchihashi
IPC分类号： G06F13/28 , G06F13/30
CPC分类号： G06F13/30
摘要： A direct memory access controller has a data assembly function by means of a single temporary register. This single register used for a number of channels replaces temporary registers which have been necessary for the respective channels to carry out channel transition during data assembly. By controlling channel transition during data assembly, it is possible to carry out DMA transfers in which channel transition is made during data assembly, thereby preventing an increase in the chip size.
摘要翻译：直接存储器访问控制器通过单个临时寄存器具有数据组合功能。用于多个通道的单个寄存器替代了在数据组合期间各个通道执行通道转换所必需的临时寄存器。通过在数据组合期间控制信道转换，可以执行在数据组合期间进行信道转换的DMA传输，从而防止芯片尺寸的增加。

2. 发明授权

US5089987A Refresh control circuit 失效
标题翻译：刷新控制电路
公开(公告)号：US5089987A
公开(公告)日：1992-02-18
申请号：US475665
申请日：1990-02-06
申请人： Yuichi Nakao , Hideharu Toyomoto
发明人： Yuichi Nakao , Hideharu Toyomoto
IPC分类号： G11C11/406
CPC分类号： G11C11/406
摘要： A refresh control circuit for a processor which is connected to dynamic random access memory via an address bus, a data bus and control signal lines. A refresh control signal is output at predetermined intervals to refresh the dynamic random access memory. The refresh control circuit includes control circuitry and an address generator. The address generator latches a value received from the control circuitry. Based on such latched value, a refresh address is changed by the N-th power of 2, N corresponding to the number of memory banks of the dynamic random access memory.
摘要翻译：一种用于经由地址总线，数据总线和控制信号线连接到动态随机存取存储器的处理器的刷新控制电路。以预定间隔输出刷新控制信号以刷新动态随机存取存储器。刷新控制电路包括控制电路和地址发生器。地址生成器锁存从控制电路接收的值。基于这样的锁存值，刷新地址以与动态随机存取存储器的存储体组数相对应的N的次幂N改变。

3. 发明授权

US5481678A Data processor including selection mechanism for coupling internal and external request signals to interrupt and DMA controllers 失效
标题翻译：数据处理器包括用于将内部和外部请求信号耦合到中断和DMA控制器的选择机制
公开(公告)号：US5481678A
公开(公告)日：1996-01-02
申请号：US92021
申请日：1993-07-12
申请人： Hiroyuki Kondo , Yuichi Nakao , Kazumi Koyama
发明人： Hiroyuki Kondo , Yuichi Nakao , Kazumi Koyama
IPC分类号： G06F13/00 , G06F13/32 , H04L29/10
CPC分类号： G06F13/32
摘要： A data processor includes an interrupt control unit (102); a direct memory access control unit (103); a selection unit (104) for selecting a connection of ready and error signals from a serial communication control unit and external interrupt and DMA request signals with interrupt inputs to the interrupt and the DMA control units; and a selection setting unit (105) for setting a selection mode of the selection unit, thereby making possible to not only switch between a process by interrupt and a process by DMA transfer by programming according to the application but also make efficient use of the hardware resources in the data processor.
摘要翻译：数据处理器包括中断控制单元（102）; 直接存储器访问控制单元（103）; 选择单元（104），用于选择来自串行通信控制单元的就绪和错误信号的连接以及具有对中断和DMA控制单元的中断输入的外部中断和DMA请求信号; 以及用于设置选择单元的选择模式的选择设置单元（105），从而不仅可以通过根据应用的编程通过中断和通过DMA传输的处理来切换处理，而且还有效地使用硬件数据处理器中的资源。

4. 发明授权

US08981440B2 Semiconductor storage device and method for manufacturing the semiconductor storage device 有权
标题翻译：半导体存储装置及半导体存储装置的制造方法
公开(公告)号：US08981440B2
公开(公告)日：2015-03-17
申请号：US13119070
申请日：2009-09-16
申请人： Yuichi Nakao
发明人： Yuichi Nakao
IPC分类号： H01L21/02 , H01L49/02 , H01L21/768 , H01L27/115
CPC分类号： H01L27/11507 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02266 , H01L21/02271 , H01L21/02274 , H01L21/32 , H01L21/76849 , H01L21/7687 , H01L27/11504 , H01L28/55 , H01L28/57 , H01L28/60 , H01L28/82
摘要： A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing apart that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.
摘要翻译：本发明的半导体存储元件的制造方法是具有下电极，强电介质膜和上电极的强电介质电容器的半导体存储元件的制造方法，其特征在于，包括：金属插塞和绝缘层中的第二金属插塞; 形成覆盖层的步骤，所述覆盖层至少覆盖与所述第一金属插塞电接触的固定的所述第二金属插塞; 在形成覆盖层之后，依次沉积下电极材料，铁电薄膜材料和上电极材料，形成沉积结构的步骤; 以及通过蚀刻除去所述沉积结构的一部分以外的其它部分使得所述沉积结构的所述部分保留在所述第一金属插塞上而形成所述强电介质电容器的步骤。

5. 发明授权

US08912657B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08912657B2
公开(公告)日：2014-12-16
申请号：US12801933
申请日：2010-07-02
申请人： Yuichi Nakao , Satoshi Kageyama , Masaru Naitou
发明人： Yuichi Nakao , Satoshi Kageyama , Masaru Naitou
IPC分类号： H01L29/72 , B23D51/12
CPC分类号： H01L23/528 , B23D51/125 , H01L21/76802 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L23/5226 , H01L23/53228 , H01L23/5329 , H01L24/05 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079
摘要： The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
摘要翻译：根据本发明的半导体器件包括半导体衬底，层叠在半导体衬底上的第一绝缘层，嵌入在第一绝缘层的引线形成区域中的第一金属布线图案，层压在第一绝缘层上的第二绝缘层层，嵌入在第二绝缘层的线形成区域中的第二金属布线图案和嵌入在与第二绝缘层的线形成区域相对的线对向区域中的第一虚拟金属图案，并且以非线与第二绝缘层的线形成区域以外的非线形成区域相对的相对区域，线对向区域和非线对置区域各自位于除非线形成区域以外的非线形成区域第一绝缘层的线形成区域。

6. 发明授权

US08102051B2 Semiconductor device having an electrode and method for manufacturing the same 有权
标题翻译：具有电极的半导体装置及其制造方法
公开(公告)号：US08102051B2
公开(公告)日：2012-01-24
申请号：US12452235
申请日：2008-06-20
申请人： Yuichi Nakao
发明人： Yuichi Nakao
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/53295 , C23C16/402 , H01L21/76808 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76843 , H01L21/76844 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device according to the present invention includes a first insulating layer made of a material containing Si and O, a groove shaped by digging down the first insulating layer, an embedded body, embedded in the groove, made of a metallic material mainly composed of Cu, a second insulating layer, stacked on the first insulating layer and the embedded body, made of a material containing Si and O, and a barrier film, formed between the embedded body and each of the first insulating layer and the second insulating layer, made of MnxSiyOz (x, y and z: numbers greater than zero).
摘要翻译：根据本发明的半导体器件包括由包含Si和O的材料制成的第一绝缘层，通过挖掘第一绝缘层而形成的凹槽，嵌入凹槽中的嵌入体，其由主要由 Cu，第二绝缘层，堆叠在由包含Si和O的材料制成的第一绝缘层和嵌入体上，以及阻挡膜，形成在嵌入体与第一绝缘层和第二绝缘层中的每一个之间，由MnxSiyOz（x，y和z：数字大于零）组成。

7. 发明申请

US20110045669A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20110045669A1
公开(公告)日：2011-02-24
申请号：US12536472
申请日：2009-08-05
申请人： Yuichi Nakao , Satoshi Kageyama
发明人： Yuichi Nakao , Satoshi Kageyama
IPC分类号： H01L21/768
CPC分类号： H01L21/76844 , H01L21/76831 , H01L21/7684 , H01L21/76862 , H01L21/76864 , H01L21/76867 , H01L21/76877 , H01L21/76883 , H01L2221/1089
摘要： The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
摘要翻译：根据本发明的制造半导体器件的方法包括：绝缘层形成步骤，形成由包含Si和O的绝缘材料制成的绝缘层; 在所述绝缘层中形成槽的槽形成工序; 通过溅射用MnO x（x：数大于零）的金属膜覆盖槽的内表面的金属膜施加步骤; 以及在金属膜上形成由主要由Cu构成的金属材料制成的Cu线的线形成工序。

8. 发明申请

US20100270686A1 Semiconductor device 有权
公开(公告)号：US20100270686A1
公开(公告)日：2010-10-28
申请号：US12801933
申请日：2010-07-02
申请人： Yuichi Nakao , Satoshi Kageyama , Masaru Naitou
发明人： Yuichi Nakao , Satoshi Kageyama , Masaru Naitou
IPC分类号： H01L29/40
CPC分类号： H01L23/528 , B23D51/125 , H01L21/76802 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L23/5226 , H01L23/53228 , H01L23/5329 , H01L24/05 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079
摘要： The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

9. 发明授权

US07781863B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US07781863B2
公开(公告)日：2010-08-24
申请号：US12007084
申请日：2008-01-07
申请人： Ryotaro Yagi , Yuichi Nakao , Isamu Nishimura
发明人： Ryotaro Yagi , Yuichi Nakao , Isamu Nishimura
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.

10. 发明授权

US07777340B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07777340B2
公开(公告)日：2010-08-17
申请号：US11979728
申请日：2007-11-07
申请人： Yuichi Nakao , Satoshi Kageyama , Masaru Naitou
发明人： Yuichi Nakao , Satoshi Kageyama , Masaru Naitou
IPC分类号： H01L29/72
CPC分类号： H01L23/522 , H01L21/3212 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05094 , H01L2224/05554 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48624 , H01L2224/48647 , H01L2224/48699 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
摘要翻译：根据本发明的半导体器件包括半导体衬底，层叠在半导体衬底上的第一绝缘层，嵌入在第一绝缘层的引线形成区域中的第一金属布线图案，层压在第一绝缘层上的第二绝缘层层，嵌入在第二绝缘层的线形成区域中的第二金属布线图案和嵌入在与第二绝缘层的线形成区域相对的线对向区域中的第一虚拟金属图案，并且以非线与第二绝缘层的线形成区域以外的非线形成区域相对的相对区域，线对向区域和非线对置区域各自位于除非线形成区域以外的非线形成区域第一绝缘层的线形成区域。

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