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1. 发明申请

US20070284675A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070284675A1
公开(公告)日：2007-12-13
申请号：US11747785
申请日：2007-05-11
申请人： Naohiko Kimizuka , Yasushi Nakahara
发明人： Naohiko Kimizuka , Yasushi Nakahara
IPC分类号： H01L29/94
CPC分类号： H01L21/28079 , H01L29/4958
摘要： The semiconductor device includes a silicon substrate, an SiO2 film provided so as to be in contact with the upper portion of the silicon substrate, and a p-type MOSFET including a polycrystalline silicon film, which is provided so as to be in contact with the upper portion of the SiO2 film. Further, an interior of the SiO2 film or an interface of the SiO2 film with the polycrystalline silicon film is provided with a region containing at least one metallic element of Hf and Zr at an area density of not higher than 1.3×1014 atoms/cm2.
摘要翻译：半导体器件包括硅衬底，设置成与硅衬底的上部接触的SiO 2膜以及包括多晶硅膜的p型MOSFET，所述p型MOSFET包括多晶硅膜以便与SiO 2膜的上部接触。此外，SiO 2膜的内部或SiO 2膜与多晶硅膜的界面设置有包含至少一种Hf的金属元素的区域，以及 Zr的面积密度不高于1.3×10 14原子/ cm 2。

2. 发明授权

US07102183B2 MOS transistor 失效
标题翻译： MOS晶体管
公开(公告)号：US07102183B2
公开(公告)日：2006-09-05
申请号：US11001310
申请日：2004-12-02
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
IPC分类号： H01L29/78 , H01L27/108 , H01L21/336
CPC分类号： H01L29/7838 , H01L21/823807
摘要： In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
摘要翻译：在包括由高介电常数材料构成的栅极绝缘膜和由多晶硅构成的栅电极的P沟道MOS晶体管中，提供了用于防止费米能级钉扎并提供阈值电压的稳定降低的技术。 MOS晶体管用作通过将In作为P型杂质注入沟道区而形成的埋入沟道晶体管。此外，栅电极由掺杂有N型杂质的多晶硅膜构成。因此，可以有效地抑制由费米能量钉扎引起的栅极耗尽。因此，能够避免栅电极的耗尽，能够稳定地降低阈值电压。在这种情况下，由于通过向栅电极施加恒定电压而引起电荷，所以阈值电压稳定地降低。

3. 发明申请

US20050263802A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050263802A1
公开(公告)日：2005-12-01
申请号：US11129439
申请日：2005-05-16
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Ayuka Tada
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Ayuka Tada
IPC分类号： H01L27/092 , H01L21/28 , H01L21/3115 , H01L21/336 , H01L21/8238 , H01L29/51 , H01L29/76 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/31155 , H01L21/823857 , H01L29/513 , H01L29/517
摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.
摘要翻译：半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

4. 发明申请

US20050224857A1 MOS transistor 失效
标题翻译： MOS晶体管
公开(公告)号：US20050224857A1
公开(公告)日：2005-10-13
申请号：US11001310
申请日：2004-12-02
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L31/062
CPC分类号： H01L29/7838 , H01L21/823807
摘要： In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
摘要翻译：在包括由高介电常数材料构成的栅极绝缘膜和由多晶硅构成的栅电极的P沟道MOS晶体管中，提供了用于防止费米能级钉扎并提供阈值电压的稳定降低的技术。 MOS晶体管用作通过将In作为P型杂质注入沟道区而形成的埋入沟道晶体管。此外，栅电极由掺杂有N型杂质的多晶硅膜构成。因此，可以有效地抑制由费米能量钉扎引起的栅极耗尽。因此，能够避免栅电极的耗尽，能够稳定地降低阈值电压。在这种情况下，由于通过向栅电极施加恒定电压而引起电荷，所以阈值电压稳定地降低。

5. 发明授权

US06380594B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06380594B1
公开(公告)日：2002-04-30
申请号：US09688696
申请日：2000-10-17
申请人： Naohiko Kimizuka
发明人： Naohiko Kimizuka
IPC分类号： H01L2976
CPC分类号： H01L21/823857 , H01L27/0922
摘要： First and second circuit blocks are provided in a semiconductor device. The first circuit block is provided with a first complementary MOS transistor including a first P-channel MOS transistor and a first N-channel MOS transistor. The second circuit block is provided with a second complementary MOS transistor including a second P-channel MOS transistor and a second N-channel MOS transistor. The threshold voltages of the first P-channel MOS transistor and the first N-channel MOS transistor are set to be higher than those of the second P-channel MOS transistor and the second N-channel MOS transistor. A gate leakage current of the first N-channel MOS transistor in a stand-by state is set to be substantially equal to that of the first P-channel MOS transistor.
摘要翻译：第一和第二电路块设置在半导体器件中。第一电路块设置有包括第一P沟道MOS晶体管和第一N沟道MOS晶体管的第一互补MOS晶体管。第二电路块设置有包括第二P沟道MOS晶体管和第二N沟道MOS晶体管的第二互补MOS晶体管。第一P沟道MOS晶体管和第一N沟道MOS晶体管的阈值电压被设定为高于第二P沟道MOS晶体管和第二N沟道MOS晶体管的阈值电压。处于待机状态的第一N沟道MOS晶体管的栅极漏电流被设定为与第一P沟道MOS晶体管基本相等。

6. 发明申请

US20060145265A1 CMOS semiconductor device 审中-公开
标题翻译： CMOS半导体器件
公开(公告)号：US20060145265A1
公开(公告)日：2006-07-06
申请号：US11300419
申请日：2005-12-15
申请人： Yuri Masuoka , Naohiko Kimizuka , Kiyotaka Imai , Toshiyuki Iwamoto
发明人： Yuri Masuoka , Naohiko Kimizuka , Kiyotaka Imai , Toshiyuki Iwamoto
IPC分类号： H01L29/94
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/28194 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518
摘要： While forming an N-type MOSFET 118 and a P-type MOSFET 120 within regions operating using the same power supply voltage, thickness of a gate insulating film 106a of an N-type MOSFET 118 is made to be thicker than thickness of a gate insulating film 106b of a P-type MOSFET 120.
摘要翻译：在使用相同电源电压工作的区域内形成N型MOSFET 118和P型MOSFET 120时，使N型MOSFET118的栅极绝缘膜106a的厚度比栅极厚度厚 P型MOSFET120的绝缘膜106b。

7. 发明申请

US20050253181A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050253181A1
公开(公告)日：2005-11-17
申请号：US11129440
申请日：2005-05-16
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Masayuki Terai
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Masayuki Terai
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L31/119
CPC分类号： H01L29/517 , H01L21/823857 , H01L29/4916 , H01L29/513 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.
摘要翻译：半导体器件100包括硅衬底102，包括形成在硅衬底102上的第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数的P型MOSFET 120 膜112和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。第一高介电常数膜111和第二高介电常数膜112包含从由Hf和Zr组成的组中选择的一种或多种元素。

8. 发明授权

US06853037B2 Fabrication of low power CMOS device with high reliability 失效
标题翻译：制造具有高可靠性的低功耗CMOS器件
公开(公告)号：US06853037B2
公开(公告)日：2005-02-08
申请号：US09872007
申请日：2001-06-04
申请人： Tomohiko Kudo , Naohiko Kimizuka
发明人： Tomohiko Kudo , Naohiko Kimizuka
IPC分类号： H01L27/092 , H01L21/316 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/8238
摘要： A semiconductor device includes a relatively lower threshold level MOSFET and relatively higher threshold level MOSFETs of n- and p-types. The higher threshold level MOSFETs have gate oxide films which is thicker than that of the lower threshold level MOSFET and, in addition, the gate oxide film of the higher threshold level MOSFET of n-type is thicker than that of the higher threshold level MOSFET of p-type. To fabricate the semiconductor device, implantation treatments of fluorine ions are carried out before the gate oxide treatment. Specifically, as for the higher threshold level MOSFETs of n- and p-types, implantation treatments of fluorine ions are independently carried out with unique implantation conditions.
摘要翻译：半导体器件包括相对较低的阈值电平MOSFET和n型和p型相对较高的阈值级MOSFET。较高阈值电平的MOSFET具有比下限阈值MOSFET厚的栅极氧化膜，此外，n型较高阈值电平MOSFET的栅极氧化膜比较高阈值电平MOSFET的栅极氧化膜厚 p型。为了制造半导体器件，在栅氧化物处理之前进行氟离子的注入处理。具体来说，对于n型和p型的较高阈值电平的MOSFET，独立的注入条件独立地进行氟离子的注入处理。

9. 发明授权

US06756635B2 Semiconductor substrate including multiple nitrided gate insulating films 失效
标题翻译：半导体衬底包括多个氮化栅绝缘膜
公开(公告)号：US06756635B2
公开(公告)日：2004-06-29
申请号：US10166189
申请日：2002-06-10
申请人： Yuri Yasuda , Naohiko Kimizuka
发明人： Yuri Yasuda , Naohiko Kimizuka
IPC分类号： H01L29792
CPC分类号： H01L21/823462 , H01L21/28176 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L21/3145 , H01L29/513 , H01L29/518
摘要： A silicon oxide film with a film thickness of 5 to 7 nm is formed on a first region, a silicon oxynitride film with a film thickness of 2 to 3 nm, and a nitrogen concentration of 1 to 3 atom % is formed on a second region, and a silicon oxynitride film with a film thickness of 1 to 2 nm, and a nitrogen concentration of 3 to 5 atom % is formed on a third region on a silicon substrate. Then, radical nitriding is applied to the silicon oxide film, and the silicon oxynitride films.
摘要翻译：在第一区域上形成膜厚为5〜7nm的氧化硅膜，在第二区域形成膜厚为2〜3nm，氮浓度为1〜3原子％的氮氧化硅膜，在硅衬底的第三区域上形成膜厚为1〜2nm，氮浓度为3〜5原子％的氮氧化硅膜。然后，对氧化硅膜和氮氧化硅膜施加自由基渗氮。

10. 发明授权

US06388504B1 Integrated circuit device with switching between active mode and standby mode controlled by digital circuit 失效
标题翻译：集成电路器件，由数字电路控制的有源模式和待机模式之间切换
公开(公告)号：US06388504B1
公开(公告)日：2002-05-14
申请号：US09663356
申请日：2000-09-15
申请人： Yoshiro Goto , Kiyotaka Imai , Naohiko Kimizuka
发明人： Yoshiro Goto , Kiyotaka Imai , Naohiko Kimizuka
IPC分类号： H03K301
CPC分类号： H01L21/823462 , H03K19/0016
摘要： In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.
摘要翻译：在集成电路器件中，具有最厚栅极绝缘膜的第三晶体管以高电压驱动，从而以最小的栅极漏电流高速运行。具有最薄栅极绝缘膜的第一晶体管和没有最薄栅极绝缘膜的第二晶体管以低电压驱动，第二晶体管始终被驱动，并且第一晶体管被适当地停止。第二晶体管以低速并且具有最小的栅极泄漏电流恒定地工作，并且具有显着的栅极泄漏电流的第一晶体管在适当的时候停止时以高速运行。

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