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1. 发明授权

US06388504B1 Integrated circuit device with switching between active mode and standby mode controlled by digital circuit 失效
标题翻译：集成电路器件，由数字电路控制的有源模式和待机模式之间切换
公开(公告)号：US06388504B1
公开(公告)日：2002-05-14
申请号：US09663356
申请日：2000-09-15
申请人： Yoshiro Goto , Kiyotaka Imai , Naohiko Kimizuka
发明人： Yoshiro Goto , Kiyotaka Imai , Naohiko Kimizuka
IPC分类号： H03K301
CPC分类号： H01L21/823462 , H03K19/0016
摘要： In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.
摘要翻译：在集成电路器件中，具有最厚栅极绝缘膜的第三晶体管以高电压驱动，从而以最小的栅极漏电流高速运行。具有最薄栅极绝缘膜的第一晶体管和没有最薄栅极绝缘膜的第二晶体管以低电压驱动，第二晶体管始终被驱动，并且第一晶体管被适当地停止。第二晶体管以低速并且具有最小的栅极泄漏电流恒定地工作，并且具有显着的栅极泄漏电流的第一晶体管在适当的时候停止时以高速运行。

2. 发明授权

US06664148B2 Integrated circuit device with switching between active mode and standby mode controlled by digital circuit 有权
公开(公告)号：US06664148B2
公开(公告)日：2003-12-16
申请号：US10073103
申请日：2002-02-12
申请人： Yoshiro Goto , Kiyotaka Imai , Naohiko Kimizuka
发明人： Yoshiro Goto , Kiyotaka Imai , Naohiko Kimizuka
IPC分类号： H01L2100
CPC分类号： H01L21/823462 , H03K19/0016
摘要： In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

3. 发明申请

US20060043497A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060043497A1
公开(公告)日：2006-03-02
申请号：US11210873
申请日：2005-08-25
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto
IPC分类号： H01L29/76
CPC分类号： H01L29/518 , H01L21/0214 , H01L21/02142 , H01L21/2652 , H01L21/2658 , H01L21/28185 , H01L21/28238 , H01L21/3115 , H01L21/3141 , H01L21/31645 , H01L21/823807 , H01L21/823828 , H01L21/823842 , H01L29/1033
摘要： Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor device 100 has a silicon substrate 101 and a P-type MOSFET 103 comprising a SiON film 113 formed on the silicon substrate 101, and a polycrystalline silicon film 106. Any one of, or two or more of metals selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W are allowed to reside at the interface 115 between the polycrystalline silicon film 106 and the SiON film 113, and concentration of the metal(s) at the interface 115 is adjusted to 5×1013 atoms/cm2 or more and less than 1.4×1015 atoms/cm2.
摘要翻译：与仅通过将杂质掺杂到沟道区域中的阈值电压的常规调节相比，场效应晶体管的阈值电压被成功地用较小剂量的杂质调节。半导体器件100具有硅衬底101和包括形成在硅衬底101上的SiON膜113的P型MOSFET 103和多晶硅膜106.选自以下的金属中的任何一种或两种以上选自的Hf，Zr，Al，La，Pr，Y，Ti，Ta和W被放置在多晶硅膜106和SiON膜113之间的界面115处，并且界面115处的金属的浓度被调整到5×10 13原子/ cm 2以上且小于1.4×10 15原子/ cm 2以上。

4. 发明授权

US07102183B2 MOS transistor 失效
标题翻译： MOS晶体管
公开(公告)号：US07102183B2
公开(公告)日：2006-09-05
申请号：US11001310
申请日：2004-12-02
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
IPC分类号： H01L29/78 , H01L27/108 , H01L21/336
CPC分类号： H01L29/7838 , H01L21/823807
摘要： In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
摘要翻译：在包括由高介电常数材料构成的栅极绝缘膜和由多晶硅构成的栅电极的P沟道MOS晶体管中，提供了用于防止费米能级钉扎并提供阈值电压的稳定降低的技术。 MOS晶体管用作通过将In作为P型杂质注入沟道区而形成的埋入沟道晶体管。此外，栅电极由掺杂有N型杂质的多晶硅膜构成。因此，可以有效地抑制由费米能量钉扎引起的栅极耗尽。因此，能够避免栅电极的耗尽，能够稳定地降低阈值电压。在这种情况下，由于通过向栅电极施加恒定电压而引起电荷，所以阈值电压稳定地降低。

5. 发明申请

US20050263802A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050263802A1
公开(公告)日：2005-12-01
申请号：US11129439
申请日：2005-05-16
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Ayuka Tada
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Ayuka Tada
IPC分类号： H01L27/092 , H01L21/28 , H01L21/3115 , H01L21/336 , H01L21/8238 , H01L29/51 , H01L29/76 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/31155 , H01L21/823857 , H01L29/513 , H01L29/517
摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.
摘要翻译：半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

6. 发明申请

US20050224857A1 MOS transistor 失效
标题翻译： MOS晶体管
公开(公告)号：US20050224857A1
公开(公告)日：2005-10-13
申请号：US11001310
申请日：2004-12-02
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L31/062
CPC分类号： H01L29/7838 , H01L21/823807
摘要： In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
摘要翻译：在包括由高介电常数材料构成的栅极绝缘膜和由多晶硅构成的栅电极的P沟道MOS晶体管中，提供了用于防止费米能级钉扎并提供阈值电压的稳定降低的技术。 MOS晶体管用作通过将In作为P型杂质注入沟道区而形成的埋入沟道晶体管。此外，栅电极由掺杂有N型杂质的多晶硅膜构成。因此，可以有效地抑制由费米能量钉扎引起的栅极耗尽。因此，能够避免栅电极的耗尽，能够稳定地降低阈值电压。在这种情况下，由于通过向栅电极施加恒定电压而引起电荷，所以阈值电压稳定地降低。

7. 发明授权

US07754570B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07754570B2
公开(公告)日：2010-07-13
申请号：US11210873
申请日：2005-08-25
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto
IPC分类号： H01L21/336
CPC分类号： H01L29/518 , H01L21/0214 , H01L21/02142 , H01L21/2652 , H01L21/2658 , H01L21/28185 , H01L21/28238 , H01L21/3115 , H01L21/3141 , H01L21/31645 , H01L21/823807 , H01L21/823828 , H01L21/823842 , H01L29/1033
摘要： Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor device 100 has a silicon substrate 101 and a P-type MOSFET 103 comprising a SiON film 113 formed on the silicon substrate 101, and a polycrystalline silicon film 106. Any one of, or two or more of metals selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W are allowed to reside at the interface 115 between the polycrystalline silicon film 106 and the SiON film 113, and concentration of the metal(s) at the interface 115 is adjusted to 5×1013 atoms/cm2 or more and less than 1.4×1015 atoms/cm2.
摘要翻译：与仅通过将杂质掺杂到沟道区域中的阈值电压的常规调节相比，场效应晶体管的阈值电压被成功地用较小剂量的杂质调节。半导体器件100具有硅衬底101和包括形成在硅衬底101上的SiON膜113的P型MOSFET 103和多晶硅膜106.选自以下的金属中的任何一种或两种以上选自的Hf，Zr，Al，La，Pr，Y，Ti，Ta和W被放置在多晶硅膜106和SiON膜113之间的界面115处，并且界面115处的金属的浓度调整为5×1013原子/ cm 2以上且小于1.4×1015原子/ cm 2。

8. 发明授权

US07238996B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07238996B2
公开(公告)日：2007-07-03
申请号：US11129439
申请日：2005-05-16
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Ayuka Tada
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Ayuka Tada
IPC分类号： H01L29/70
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/31155 , H01L21/823857 , H01L29/513 , H01L29/517
摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.
摘要翻译：半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

9. 发明申请

US20060252264A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060252264A1
公开(公告)日：2006-11-09
申请号：US11416209
申请日：2006-05-03
申请人： Naohiko Kimizuka , Kiyotaka Imai
发明人： Naohiko Kimizuka , Kiyotaka Imai
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/28518 , H01L21/28097 , H01L29/66507 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate and containing a gate electrode; impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of the gate electrode, of a region on which the semiconductor element is formed of the semiconductor substrate; first silicide films formed respectively at the surface of the impurity diffusion layers, composed of a silicide compound of a first metal; and a second silicide film, formed at least at the surface of the gate electrode, composed of a silicide compound of a second metal different to the first metal. The silicide compound of the second metal has a silicidation temperature lower than the silicidation temperature of the silicide compound of the first metal.
摘要翻译：半导体器件包括：半导体衬底; 半导体元件，形成在所述半导体基板上并且包含栅电极; 在半导体衬底上形成有半导体元件的区域的栅电极的栅极长度方向的截面形成在两侧的杂质扩散层; 分别在由第一金属的硅化物构成的杂质扩散层的表面上形成的第一硅化物膜; 以及第二硅化物膜，至少形成在栅电极的表面，由与第一金属不同的第二金属的硅化物化合物构成。第二金属的硅化物化合物的硅化温度低于第一金属的硅化物的硅化温度。

10. 发明申请

US20060145265A1 CMOS semiconductor device 审中-公开
标题翻译： CMOS半导体器件
公开(公告)号：US20060145265A1
公开(公告)日：2006-07-06
申请号：US11300419
申请日：2005-12-15
申请人： Yuri Masuoka , Naohiko Kimizuka , Kiyotaka Imai , Toshiyuki Iwamoto
发明人： Yuri Masuoka , Naohiko Kimizuka , Kiyotaka Imai , Toshiyuki Iwamoto
IPC分类号： H01L29/94
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/28194 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518
摘要： While forming an N-type MOSFET 118 and a P-type MOSFET 120 within regions operating using the same power supply voltage, thickness of a gate insulating film 106a of an N-type MOSFET 118 is made to be thicker than thickness of a gate insulating film 106b of a P-type MOSFET 120.
摘要翻译：在使用相同电源电压工作的区域内形成N型MOSFET 118和P型MOSFET 120时，使N型MOSFET118的栅极绝缘膜106a的厚度比栅极厚度厚 P型MOSFET120的绝缘膜106b。

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