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1. 发明授权

US07453724B2 Flash memory device having improved program rate 有权
标题翻译：闪存设备具有改进的编程速率
公开(公告)号：US07453724B2
公开(公告)日：2008-11-18
申请号：US11931992
申请日：2007-10-31
申请人： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
发明人： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0475 , G11C16/3454 , G11C16/3459
摘要： A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收标识阵列中的多个存储单元的编程窗口。在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

2. 发明授权

US07307878B1 Flash memory device having improved program rate 有权
标题翻译：闪存设备具有改进的编程速率
公开(公告)号：US07307878B1
公开(公告)日：2007-12-11
申请号：US11212850
申请日：2005-08-29
申请人： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
发明人： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0475 , G11C16/3454 , G11C16/3459
摘要： A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收标识阵列中的多个存储单元的编程窗口。在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

3. 发明申请

US20070165458A1 Random cache read using a double memory 有权
标题翻译：使用双内存读取随机缓存
公开(公告)号：US20070165458A1
公开(公告)日：2007-07-19
申请号：US11332241
申请日：2006-01-17
申请人： Nancy Leong , Sachit Chandra , Hounien Chen
发明人： Nancy Leong , Sachit Chandra , Hounien Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G06F12/0893 , G06F2212/2022 , G11C7/1039
摘要： A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.
摘要翻译：诸如闪存的非易失性存储器被配置为执行随机的多页读取操作。存储器可以包括非易失性存储器单元的核心阵列和用于接收随机多页读取操作的指示的输入线。此外，存储器可以包括耦合到核心阵列的多级易失性存储器，其被配置为以流水线方式从核心阵列同时处理多个数据页面。输出线耦合到多级易失性存储器并从存储器件输出数据页面。

4. 发明授权

US07433228B2 Multi-bit flash memory device having improved program rate 有权
标题翻译：具有改进的程序速率的多位闪存设备
公开(公告)号：US07433228B2
公开(公告)日：2008-10-07
申请号：US11229519
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Hounien Chen , Sachit Chandra , Nian Yang
发明人： Tiao-Hua Kuo , Nancy Leong , Hounien Chen , Sachit Chandra , Nian Yang
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/10
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源区域和漏极区域。该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在第二个地区的利率要高得多。

5. 发明授权

US07423915B2 Random cache read using a double memory 有权
标题翻译：使用双内存读取随机缓存
公开(公告)号：US07423915B2
公开(公告)日：2008-09-09
申请号：US11332241
申请日：2006-01-17
申请人： Nancy Leong , Sachit Chandra , Hounien Chen
发明人： Nancy Leong , Sachit Chandra , Hounien Chen
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C16/26 , G06F12/0893 , G06F2212/2022 , G11C7/1039
摘要： A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.
摘要翻译：诸如闪存的非易失性存储器被配置为执行随机的多页读取操作。存储器可以包括非易失性存储器单元的核心阵列和用于接收随机多页读取操作的指示的输入线。此外，存储器可以包括耦合到核心阵列的多级易失性存储器，其被配置为以流水线方式从核心阵列同时处理多个数据页面。输出线耦合到多级易失性存储器并从存储器件输出数据页面。

6. 发明申请

US20070064480A1 Multi-bit flash memory device having improved program rate 有权
标题翻译：具有改进的程序速率的多位闪存设备
公开(公告)号：US20070064480A1
公开(公告)日：2007-03-22
申请号：US11229519
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Hounien Chen , Sachit Chandra , Nian Yang
发明人： Tiao-Hua Kuo , Nancy Leong , Hounien Chen , Sachit Chandra , Nian Yang
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/10
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源区域和漏极区域。该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在第二个地区的利率要高得多。

7. 发明申请

US20070035991A1 Read mode for flash memory 有权
标题翻译：闪存读取模式
公开(公告)号：US20070035991A1
公开(公告)日：2007-02-15
申请号：US11189923
申请日：2005-07-27
申请人： Hounien Chen , Nancy Leong
发明人： Hounien Chen , Nancy Leong
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.
摘要翻译：一种用于读取包括存储器单元阵列的非易失性存储器阵列的方法，每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域，包括在地址寄存器处接收读取命令包括存储器单元阵列中的存储器单元的地址以及关于读取命令是全页读取命令还是部分页面读取命令的指示。识别包括接收到的地址的页面的起始地址，其中页面包括存储器单元阵列中的多行存储器单元。地址寄存器将重置为页面的起始地址。确定页面中的所有存储单元是否被编程。如果确定页面中的所有存储器单元都未被编程，则输出指示页面的非编程状态的数据。

8. 发明授权

US08107294B2 Read mode for flash memory 有权
标题翻译：闪存读取模式
公开(公告)号：US08107294B2
公开(公告)日：2012-01-31
申请号：US12730452
申请日：2010-03-24
申请人： Hounien Chen , Nancy S. Leong
发明人： Hounien Chen , Nancy S. Leong
IPC分类号： G11C16/04 , G11C16/06 , G11C16/26 , G11C16/08
CPC分类号： G11C16/26
摘要： A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.
摘要翻译：一种用于读取包括存储器单元阵列的非易失性存储器阵列的方法，每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域，包括在地址寄存器处接收读取命令包括存储器单元阵列中的存储器单元的地址以及关于读取命令是全页读取命令还是部分页面读取命令的指示。识别包括接收到的地址的页面的起始地址，其中页面包括存储器单元阵列中的多行存储器单元。地址寄存器将重置为页面的起始地址。确定页面中的所有存储单元是否被编程。如果确定页面中的所有存储器单元都未被编程，则输出指示页面的非编程状态的数据。

9. 发明申请

US20070076513A1 Decoder for memory device with loading capacitor 审中-公开
标题翻译：带加载电容的存储器解码器
公开(公告)号：US20070076513A1
公开(公告)日：2007-04-05
申请号：US11243078
申请日：2005-10-04
申请人： Nian Yang , Fan Lai , Hounien Chen
发明人： Nian Yang , Fan Lai , Hounien Chen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C16/0416 , G11C16/08
摘要： A decoder system for a memory device includes a high voltage pump, a high voltage switch, and a loading capacitor. The high voltage pump generates a boost voltage, and the high voltage switch couples one of the boost voltage or a low voltage to a line of the memory device. The loading capacitor is coupled to a node between the high voltage pump and the high voltage switch to minimize voltage dipping of the boost voltage.
摘要翻译：用于存储器件的解码器系统包括高压泵，高压开关和负载电容器。高压泵产生升压电压，高电压开关将升压或低电压中的一个耦合到存储器件的一行。加载电容器耦合到高压泵和高压开关之间的节点，以最小化升压电压的电压浸没。

10. 发明授权

US07706183B2 Read mode for flash memory 有权
标题翻译：闪存读取模式
公开(公告)号：US07706183B2
公开(公告)日：2010-04-27
申请号：US11189923
申请日：2005-07-27
申请人： Hounien Chen , Nancy S. Leong
发明人： Hounien Chen , Nancy S. Leong
IPC分类号： G11C16/26 , G11C16/06 , G11C7/10 , G11C8/12 , G06F13/00
CPC分类号： G11C16/26
摘要： A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.
摘要翻译：一种用于读取包括存储器单元阵列的非易失性存储器阵列的方法，每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域，包括在地址寄存器处接收读取命令包括存储器单元阵列中的存储器单元的地址以及关于读取命令是全页读取命令还是部分页面读取命令的指示。识别包括接收到的地址的页面的起始地址，其中页面包括存储器单元阵列中的多行存储器单元。地址寄存器将重置为页面的起始地址。确定页面中的所有存储单元是否被编程。如果确定页面中的所有存储器单元都未被编程，则输出指示页面的非编程状态的数据。

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