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    • 7. 发明申请
    • INTEGRATED JUNCTION AND JUNCTIONLESS NANOTRANSISTORS
    • 集成连接和无连接的纳米器件
    • US20140145273A1
    • 2014-05-29
    • US14088650
    • 2013-11-25
    • Sung-Dae SukChangwoo OhSungil Park
    • Sung-Dae SukChangwoo OhSungil Park
    • H01L27/088
    • H01L27/0924H01L21/823412H01L21/823431H01L21/823807H01L21/823821H01L27/0883H01L27/0886H01L27/0922
    • Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor.
    • 包括第一晶体管和第二晶体管的半导体器件集成在基板上。 第一和第二晶体管中的每一个包括纳米尺寸的有源区,其包括设置在纳米尺寸有源区的相应端部中的源极和漏极区以及设置在源极和漏极区之间的沟道形成区。 第一晶体管的源极和漏极区域具有与第二晶体管相同的导电类型,并且第二晶体管具有低于第一晶体管的阈值电压的阈值电压。 第二晶体管的沟道形成区域可以包括均匀掺杂区域,其导电类型与第二晶体管的源极和漏极区域相同,并且与第一晶体管的沟道形成区域不同。