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    • 4. 发明授权
    • Combined transmitter
    • 组合发射机
    • US07471285B2
    • 2008-12-30
    • US10976134
    • 2004-10-28
    • Yu-Feng ChengWen-Bo LiuKen-Ming LiVai-Hang AuZhen-Yu Song
    • Yu-Feng ChengWen-Bo LiuKen-Ming LiVai-Hang AuZhen-Yu Song
    • G09G5/00
    • H04L25/0272
    • A combined transmission unit for TMDS signals and LVDS signals. A first (LVDS) transmission unit comprises a set of first input terminals to receive first data, and a second (TMDS) transmission unit comprises a set of second input terminals to receive second data. A switching controller enables the first transmission unit to transmit the first data to the first external input units through a pair of signal lines coupled to a set of common output line or enables the second transmission unit to transmit the second data to the second external input units through a pair of signal lines coupled to the set of common output line, according to a mode selection signal.
    • 用于TMDS信号和LVDS信号的组合传输单元。 第一(LVDS)传输单元包括一组用于接收第一数据的第一输入端,第二(TMDS)传输单元包括一组第二输入端以接收第二数据。 开关控制器使得第一传输单元能够通过耦合到一组公共输出线的一对信号线将第一数据发送到第一外部输入单元,或使得第二传输单元能够将第二数据发送到第二外部输入单元 通过耦合到所述一组公共输出线的一对信号线,根据模式选择信号。
    • 5. 发明授权
    • Delay locked loop with common counter and method thereof
    • 延迟锁定环与公共计数器及其方法
    • US07471131B2
    • 2008-12-30
    • US11468359
    • 2006-08-30
    • Zhongding LiuZhen-Yu SongKen-Ming LiJoe BiSally Qu
    • Zhongding LiuZhen-Yu SongKen-Ming LiJoe BiSally Qu
    • H03L7/06
    • H03L7/0814
    • A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.
    • 延迟锁定环路电路,用于延迟输入时钟锁定延迟时钟。 延迟锁定环包括用于将输入时钟的频率除以数字N的分频器,以获得分频时钟;多个延迟分量,用于延迟输入时钟以根据相位而产生具有不同相位的多个延迟时钟 计数值,耦合到用于检测最终延迟时钟和输入时钟之间的相位的最终延迟分量的相位检测器,以及耦合到相位检测器和分频器的计数器,用于根据相位转换产生计数值 在最后的延迟时钟和输入时钟之间。
    • 8. 发明申请
    • DUAL-FUNCTION DRIVERS
    • 双功能驱动器
    • US20070127518A1
    • 2007-06-07
    • US11556217
    • 2006-11-03
    • Wen-Bo LiuYu-Feng ChengKen-Ming LiVai-Hang Au
    • Wen-Bo LiuYu-Feng ChengKen-Ming LiVai-Hang Au
    • H04L12/66H04L12/56
    • H04L25/0272
    • Dual-function drivers capable of outputting LVDS or TMDS differential signals by sharing output terminals under differential modes. In the dual-function driver, an input control unit receives a first input signal compliant with a first specification in a first mode and a second input signal compliant with a second specification in a second mode by sharing a pair of input terminals, and a current steering circuit comprises first and second differential pairs. The input control unit enables the first and second differential pairs to output a first differential signal compliant with the first specification through a pair of output terminals during the first mode, and the input control unit disables the first differential pair and enables the second differential pair to output a second differential signal compliant with the second specification on the pair of output terminals during the second mode.
    • 双功能驱动器能够通过在差分模式下共享输出端子来输出LVDS或TMDS差分信号。 在双功能驱动器中,输入控制单元通过共享一对输入端子接收符合第一模式的第一规格的第一输入信号和符合第二规范的第二输入信号,并且电流 转向电路包括第一和第二差分对。 所述输入控制单元使得所述第一差分对和所述第二差分对在所述第一模式期间通过一对输出端输出符合所述第一规范的第一差分信号,并且所述输入控制单元禁用所述第一差分对,并使所述第二差分对能够 在所述第二模式期间,在所述一对输出端子上输出符合所述第二规范的第二差分信号。
    • 10. 发明授权
    • Apparatus and method for on-chip jitter measurement
    • 用于片上抖动测量的装置和方法
    • US07120215B2
    • 2006-10-10
    • US10017160
    • 2001-12-12
    • Ken-Ming LiYun-Hsiang (Chris) Tsao
    • Ken-Ming LiYun-Hsiang (Chris) Tsao
    • H04L7/00
    • H04L1/205H04L7/0337
    • A jitter measurement circuit is described comprising delay elements arranged in a serially-connected chain, and first and second sets of circuitry. Each delay elements has an associated delay, an input and an output that produces a delayed version of the signal at the input. The first set of circuitry is configured to detect propagation of the significant instant of the input clock signal through each of the delay elements and produces a pulse in response thereto. The width of the pulse is approximately equal to the delay of the corresponding delay element. The second set of circuitry has one storage element corresponding to each output of the first set of circuitry, for receiving a trigger signal that is timed to correspond to a delay which is approximately half of the total delay of the chain, and for recording in the corresponding storage element any pulse that is active at the time of occurrence of the trigger signal. Thus, a jitter measurement is made based on the pulses recorded in the storage elements after a plurality of trigger signals has occurred.
    • 描述抖动测量电路,其包括布置在串联连接的链路中的延迟元件以及第一和第二组电路。 每个延迟元件具有相关联的延迟,输入和输出,其在输入端产生信号的延迟版本。 第一组电路被配置为检测通过每个延迟元件的输入时钟信号的有效瞬间的传播,并响应于此产生一个脉冲。 脉冲的宽度大致等于对应的延迟元件的延迟。 所述第二组电路具有对应于所述第一组电路的每个输出的一个存储元件,用于接收触发信号,所述触发信号被定时以对应于大约是所述链的总延迟的一半的延迟,并且用于在 相应的存储元件在触发信号发生时有效的任何脉冲。 因此,在发生多个触发信号之后,基于记录在存储元件中的脉冲进行抖动测量。