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1. 发明授权

US09043539B2 Semiconductor device having a memory and calibration circuit that selectively adjusts an impedance of an output buffer dependent upon refresh commands 有权
标题翻译：具有存储器和校准电路的半导体器件，其根据刷新命令有选择地调节输出缓冲器的阻抗
公开(公告)号：US09043539B2
公开(公告)日：2015-05-26
申请号：US12923261
申请日：2010-09-10
申请人： Nakaba Kaiwa , Yutaka Ikeda , Hiroki Fujisawa , Tetsuaki Okahiro
发明人： Nakaba Kaiwa , Yutaka Ikeda , Hiroki Fujisawa , Tetsuaki Okahiro
IPC分类号： G06F12/00 , G11C7/00 , G11C11/406 , G11C7/04 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4093
CPC分类号： G11C11/406 , G11C7/04 , G11C7/1057 , G11C7/20 , G11C11/40611 , G11C11/40626 , G11C11/4072 , G11C11/4093 , G11C2207/2254 , G11C2211/4061
摘要： A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.
摘要翻译：一种具有选择性地调节输出缓冲器的阻抗的电路的半导体器件。可以自动执行校准操作，而不从控制器发出校准命令。由于响应于已经发出预定次数的自动刷新命令执行对存储器的校准操作，因此可以确保周期性校准操作，并且在期间不会从控制器请求读取操作或写入操作校准操作。当刷新计数器指示预定值时，启动电路激活校准电路，并且当校准电路被激活时，响应于自动刷新命令禁止刷新操作。可以使用温度检测电路来改变执行校准操作的频率。

2. 发明申请

US20110066798A1 Semiconductor device having calibration circuit that adjusts an impedance of output buffer and data processing system including the same 有权
标题翻译：具有调整输出缓冲器的阻抗的校准电路的半导体器件及包括该校正电路的数据处理系统
公开(公告)号：US20110066798A1
公开(公告)日：2011-03-17
申请号：US12923261
申请日：2010-09-10
申请人： Nakaba Kaiwa , Yutaka Ikeda , Hiroki Fujisawa , Tetsuaki Okahiro
发明人： Nakaba Kaiwa , Yutaka Ikeda , Hiroki Fujisawa , Tetsuaki Okahiro
IPC分类号： G06F12/00 , G11C7/00
CPC分类号： G11C11/406 , G11C7/04 , G11C7/1057 , G11C7/20 , G11C11/40611 , G11C11/40626 , G11C11/4072 , G11C11/4093 , G11C2207/2254 , G11C2211/4061
摘要： A calibration operation can be performed automatically at a semiconductor device without issuing a calibration command from a controller. Because a calibration operation is performed in response to a fact that the auto refresh command has been issued for a predetermined number of times, a periodical calibration operation can be secured and a read operation or a write operation is not requested from a controller during a calibration operation.
摘要翻译：可以在半导体装置处自动执行校准操作，而不从控制器发出校准命令。由于响应于自动刷新命令已经发出预定次数的事实执行校准操作，所以可以确保周期性校准操作，并且在校准期间不从控制器请求读取操作或写入操作操作。

3. 发明授权

US08106676B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08106676B2
公开(公告)日：2012-01-31
申请号：US12691215
申请日：2010-01-21
申请人： Nakaba Kaiwa , Yutaka Ikeda
发明人： Nakaba Kaiwa , Yutaka Ikeda
IPC分类号： H03K19/003
CPC分类号： G11C29/02 , G01R31/31715 , G11C7/1051 , G11C7/1057 , G11C11/4093 , G11C29/022 , G11C29/025 , G11C29/028 , G11C29/50008
摘要： A semiconductor device includes a signal generating circuit that generates an impedance adjustment command signal which indicates at least one of initiation and termination of an impedance adjustment. The semiconductor device outputs an output signal in synchronism with the impedance adjustment command signal.
摘要翻译：一种半导体器件包括产生阻抗调节指令信号的信号发生电路，该阻抗调整指令信号指示阻抗调整的起始和终止中的至少一个。半导体器件与阻抗调整指令信号同步地输出输出信号。

4. 发明申请

US20100177588A1 CALIBRATION CIRCUIT AND CALIBRATION METHOD 审中-公开
标题翻译：校准电路和校准方法
公开(公告)号：US20100177588A1
公开(公告)日：2010-07-15
申请号：US12687584
申请日：2010-01-14
申请人： Nakaba Kaiwa , Yutaka Ikeda , Hideyuki Yoko
发明人： Nakaba Kaiwa , Yutaka Ikeda , Hideyuki Yoko
IPC分类号： G11C8/18 , H03L7/00
CPC分类号： G11C8/18 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A calibration circuit includes replica buffers that have a substantially same circuit configuration as at least a part of an output buffer, an oscillator circuit that generates an internal clock in response to issuance of a calibration command, and a control circuit that controls an impedance of the replica buffers in synchronization with the internal clock. According to the present invention, because a calibration operation that does not depend on an external clock is performed, even when a frequency of the external clock is changed according to an operation mode or the like, it is possible to maintain a constant period of time given to a single adjustment step or a constant time required for a series of calibration operations.
摘要翻译：校准电路包括具有与输出缓冲器的至少一部分基本相同的电路配置的复制缓冲器，响应于发出校准命令产生内部时钟的振荡器电路，以及控制电路复制缓冲器与内部时钟同步。根据本发明，由于执行不依赖于外部时钟的校准操作，即使当外部时钟的频率根据操作模式等而改变时，也可以保持恒定的时间段给予一系列校准操作所需的单个调整步骤或恒定时间。

5. 发明授权

US08018246B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08018246B2
公开(公告)日：2011-09-13
申请号：US12698567
申请日：2010-02-02
申请人： Nakaba Kaiwa , Yutaka Ikeda
发明人： Nakaba Kaiwa , Yutaka Ikeda
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/0005 , G11C7/1051 , G11C7/1057 , G11C11/4096 , G11C2207/2254
摘要： A device includes a first circuit and an adjustment circuit. The adjustment circuit performs an adjustment on impedance of the first circuit. The adjustment circuit discontinues the adjustment on impedance while the first circuit is in an activated state.
摘要翻译：一种装置包括第一电路和调整电路。调整电路对第一电路的阻抗进行调整。当第一电路处于激活状态时，调节电路中断阻抗调整。

6. 发明授权

US09152594B2 Semiconductor memory device for high speed reading and writing 有权
标题翻译：半导体存储器件，用于高速读写
公开(公告)号：US09152594B2
公开(公告)日：2015-10-06
申请号：US13547799
申请日：2012-07-12
申请人： Nakaba Kaiwa , Yoshinori Matsui
发明人： Nakaba Kaiwa , Yoshinori Matsui
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/40 , G06F13/4059
摘要： A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus connecting the plurality of memory cell arrays and the peripheral circuit section. The peripheral circuit section includes external input/output buffers, and bus interface circuits. The bus interface circuits execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers. The bus interface circuits are densely arranged between the internal bus and the input/output buffers, so that a width d1 of the area of the plurality of bus interface circuits being arranged is narrower than a width d2 of the area of the external input/output buffers being arranged and a bus width maximum value d3 of the internal bus.
摘要翻译：半导体存储器件包括存储单元阵列部分，其包括多个存储单元阵列，外围电路部分和连接多个存储单元阵列和外围电路部分的内部总线。外围电路部分包括外部输入/输出缓冲器和总线接口电路。总线接口电路通过内部总线和通过多个外部输入/输出缓冲器以串行方式输入/输出的数据在与存储单元阵列并行输入/输出的数据之间执行转换。总线接口电路密集地布置在内部总线和输入/输出缓冲器之间，使得布置的多个总线接口电路的区域的宽度d1比外部输入/输出区域的宽度d2窄布置的缓冲器和内部总线的总线宽度最大值d3。

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