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1. 发明授权

US5819157A Reduced power tuner chip with integrated voltage regulator for a satellite receiver system 失效
标题翻译：用于卫星接收机系统的集成稳压器的功率调谐器芯片
公开(公告)号：US5819157A
公开(公告)日：1998-10-06
申请号：US878354
申请日：1997-06-18
申请人： Nadav Ben-Efraim , Christopher Keate
发明人： Nadav Ben-Efraim , Christopher Keate
IPC分类号： H04B1/16 , H03J7/06 , H04B1/30 , H04H40/90 , H04N5/21 , H04N5/44 , H04N5/455 , H04N7/20
CPC分类号： H04H40/90 , H03J7/065 , H04N21/426 , H04N21/6143 , H04N5/211 , H04N5/455 , H04N7/20 , H04B1/30 , H04N5/4401
摘要： An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip has reduced-power features which allow the incorporation of an on-chip voltage regulator. The tuner chip is a direct conversion tuner with on-chip tuning frequency generation and reduced power interface signals. The on-chip voltage regulator provides a constant power supply for nonlinear components of the tuner and frequency generation circuitry to minimize phase noise. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip includes an on-chip voltage regulator, in addition to a tuning oscillator, a charge pump, a downconverter, and a lowpass filter. The on-chip voltage regulator is operable to provide a stable power supply to the tuning oscillator and the charge pump. The tuning oscillator is coupled to a tank circuit having an adjustable resonance frequency, and the charge pump is coupled to the tank circuit to control the resonance frequency. The downconverter receives a tuning frequency provided by the tuning oscillator, receives a receive signal, and combines the tuning frequency signal with the receive signal to produce a product signal. The lowpass filter acts to convert the product signal into a baseband signal, which may then be provided as a differential output signal.
摘要翻译：具有调谐器芯片和解调器/解码器芯片的改进的DBS接收机前端架构。调谐器芯片具有降低功率特征，其允许并入片上电压调节器。调谐器芯片是具有片上调谐频率生成和降低的电源接口信号的直接转换调谐器。片上稳压器为调谐器和频率发生电路的非线性元件提供恒定的电源，以最小化相位噪声。广义而言，本发明涉及一种DBS接收器前端，其包括调谐器芯片和解调器/解码器芯片。除了调谐振荡器，电荷泵，下变频器和低通滤波器之外，调谐器芯片还包括片上稳压器。片上稳压器可操作以向调谐振荡器和电荷泵提供稳定的电源。调谐振荡器耦合到具有可调节谐振频率的振荡电路，并且电荷泵耦合到储能电路以控制谐振频率。下变频器接收由调谐振荡器提供的调谐频率，接收接收信号，并将调谐频率信号与接收信号组合以产生乘积信号。低通滤波器用于将产品信号转换为基带信号，然后可将其作为差分输出信号提供。

2. 发明授权

US6134282A Method for lowpass filter calibration in a satellite receiver 失效
标题翻译：卫星接收机低通滤波器校准方法
公开(公告)号：US6134282A
公开(公告)日：2000-10-17
申请号：US878329
申请日：1997-06-18
申请人： Nadav Ben-Efraim , Christopher Keate
发明人： Nadav Ben-Efraim , Christopher Keate
IPC分类号： H04B1/26 , H03J3/08 , H03J7/06 , H03J7/08 , H04B1/10 , H04B1/16 , H04B15/04 , H04H40/90
CPC分类号： H04H40/90 , H03J3/08 , H03J7/065 , H03J7/08 , H04B1/1027 , H04B15/04 , H04B2001/1054 , H04B2215/064
摘要： An improved satellite receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip includes a lowpass filter having a configurable cutoff frequency, and the tuner chip uses a frequency signal to provide accurate adjustment of the cutoff frequency. A clock signal having a clock frequency is converted into a control voltage which determines the cutoff frequency of the lowpass filter. Consequently, the cutoff frequency may be increased by increasing the clock frequency, or decreased by decreasing the clock frequency. This configuration provides for improved cutoff frequency control in the presence of signal interference.
摘要翻译：具有调谐器芯片和解调器/解码器芯片的改进的卫星接收机前端架构。调谐器芯片包括具有可配置截止频率的低通滤波器，并且调谐器芯片使用频率信号来提供对截止频率的精确调整。具有时钟频率的时钟信号被转换成确定低通滤波器的截止频率的控制电压。因此，可以通过增加时钟频率来增加截止频率，或者通过降低时钟频率来减小截止频率。该配置提供了在存在信号干扰的情况下改进的截止频率控制。

3. 发明授权

US5955783A High frequency signal processing chip having signal pins distributed to minimize signal interference 失效
标题翻译：具有分配信号引脚的高频信号处理芯片以最小化信号干扰
公开(公告)号：US5955783A
公开(公告)日：1999-09-21
申请号：US878333
申请日：1997-06-18
申请人： Nadav Ben-Efraim , Christopher Keate
发明人： Nadav Ben-Efraim , Christopher Keate
IPC分类号： H01L23/28 , H03D3/00 , H03D7/16 , H04B1/08 , H04B1/30 , H04B15/00 , H04H40/90 , H01L23/34 , H01L23/48 , H01L23/52
CPC分类号： H04H40/90 , H03D3/007 , H03D7/166 , H04B1/30
摘要： A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip converts a receive signal to a baseband signal using a tuning frequency signal generated from a tank circuit. The design of a package for the tuner chip maximally spaces the pins associated with high frequency signals by placing them on opposite sides of the chip (in the case of two high frequency signal sources) or (in the case of three high frequency signal sources) in a triangle formation with widely spaced vertices wherein at least two of the pins are adjacent to corners of the package. For two or more high frequency signal sources, a good determination of pin locations can be determined according to the formula P.sub.i =C+i.multidot..left brkt-bot.N/M.right brkt-bot., i=1, . . . , M, where P.sub.i are the pin numbers, N is a total number of pins around the perimeter of the package, M is a total number of the high frequency signal sources, and C is an offset number. Where a high frequency signal source has more than one associated pin, one pin number is found from the above formula, and the associated pins are placed on adjacent pins.
摘要翻译： DBS接收机前端，包括调谐器芯片和解调器/解码器芯片。调谐器芯片使用从电路产生的调谐频率信号将接收信号转换为基带信号。用于调谐器芯片的封装的设计通过将与高频信号相关联的引脚放置在芯片的相对侧（在两个高频信号源的情况下）或（在三个高频信号源的情况下）在具有广泛间隔的顶点的三角形形状中，其中至少两个销与包装的角相邻。对于两个或更多个高频信号源，可以根据公式Pi = C + ix + 537 N / M + 540，i = 1来确定引脚位置的良好确定。。。，M，其中Pi是引脚号，N是封装周边周围的引脚总数，M是高频信号源的总数，C是偏移号。在高频信号源具有多于一个的相关引脚的情况下，从上述公式可以看到一个引脚号，并将相应的引脚放置在相邻引脚上。

4. 发明授权

US5999793A Satellite receiver tuner chip with frequency synthesizer having an externally configurable charge pump 失效
标题翻译：具有频率合成器的卫星接收机调谐器芯片具有外部可配置的电荷泵
公开(公告)号：US5999793A
公开(公告)日：1999-12-07
申请号：US878334
申请日：1997-06-18
申请人： Nadav Ben-Efraim , Christopher Keate
发明人： Nadav Ben-Efraim , Christopher Keate
IPC分类号： H03D7/00 , H03D7/16 , H03J5/02 , H03J7/02 , H03L7/089 , H03L7/193 , H04B1/16 , H04B1/18 , H04B1/26 , H04H40/90 , H04L27/00 , H04Q7/06
CPC分类号： H04H40/90 , H03D7/165 , H03J5/0272 , H03J7/02 , H03L7/0898 , H04L27/0014 , H03L7/193 , H04L2027/0032 , H04L2027/0057
摘要： The problems outlined above are in large part solved by an improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The front end includes a frequency synthesizer with an externally configurable charge pump on the tuner chip. The charge pump is coupled to a tank circuit having an adjustable resonance frequency. The resonance frequency can be adjusted over an entire octave by controlling the reverse bias voltage on a pair of varactors. A charge pump with a configurable gain is used to provide a control voltage to the tank circuit to provide a constant phase locked loop response over the frequency range of the tank circuit. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip is coupled to receive a receive signal and convert it to a baseband signal. The tuner chip includes an externally configurable charge pump, a tuning oscillator, and a downconverter. The charge pump receives binary inputs indicating a desired gain and responsively amplifies a phase difference signal by the desired gain to provide a correction signal to a loop filter. The loop filter is coupled to adjust a resonance frequency control voltage in a tank circuit according to the correction signal The tuning oscillator oscillates at the resonance frequency of the tank circuit. The downconverter receives a tuning frequency signal provided by the tuning oscillator, and combines it with a receive signal to produce a product signal.
摘要翻译：上述问题在很大程度上通过具有调谐器芯片和解调器/解码器芯片的改进的DBS接收器前端架构来解决。前端包括在调谐器芯片上具有外部配置的电荷泵的频率合成器。电荷泵耦合到具有可调共振频率的电路。通过控制一对变容二极管上的反向偏置电压，可以在整个八度音阶上调节谐振频率。具有可配置增益的电荷泵用于向储能电路提供控制电压，以在储能电路的频率范围内提供恒定的锁相环响应。广义而言，本发明涉及一种DBS接收器前端，其包括调谐器芯片和解调器/解码器芯片。调谐器芯片被耦合以接收接收信号并将其转换为基带信号。调谐器芯片包括外部可配置的电荷泵，调谐振荡器和下变频器。电荷泵接收指示期望增益的二进制输入，并且响应地将相位差信号放大所需增益，以向环路滤波器提供校正信号。环路滤波器被耦合以根据校正信号调节振荡电路中的谐振频率控制电压。调谐振荡器以谐振频率的谐振频率振荡。下变频器接收由调谐振荡器提供的调谐频率信号，并将其与接收信号组合以产生产品信号。

5. 发明授权

US5901184A Extended range voltage controlled oscillator for frequency synthesis in a satellite receiver 失效
标题翻译：用于卫星接收机频率合成的扩展范围压控振荡器
公开(公告)号：US5901184A
公开(公告)日：1999-05-04
申请号：US878335
申请日：1997-06-18
申请人： Nadav Ben-Efraim , Christopher Keate
发明人： Nadav Ben-Efraim , Christopher Keate
IPC分类号： H04B1/26 , H04B1/16 , H04H40/90 , H04L27/00 , H04L27/233 , H04L27/06 , H04H1/00
CPC分类号： H04H40/90 , H04L27/2332 , H04L2027/0032 , H04L2027/0057 , H04L2027/0069
摘要： An improved DBS receiver front end architecture having a voltage controlled oscillator for frequency synthesis. The voltage controlled oscillator includes a tank circuit having an adjustable resonance frequency which may be varied over an octave. A tuning oscillator drives the tank circuit and provides a signal having that resonance frequency to a range extender which provides a tuning frequency. When enabled, the range extender doubles the input frequency, and when disabled, simply passes the input frequency through. A feedback path provides a control voltage to the tank circuit to adjust the resonance frequency and thereby cause the tuning frequency to be a multiple of a reference frequency. The range extender extends the tuning frequency range over two octaves without a loss of frequency resolution. Broadly speaking, the present invention contemplates a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip has a frequency doubler which provides a tuning frequency signal having a frequency twice that of an input frequency signal when the doubler is enabled, and a tuning frequency signal having a frequency equal that of an input frequency signal when the doubler is disabled. The tuner chip also has a tuning oscillator which provides the input frequency, and a downconverter coupled to receive the tuning frequency signal. The downconverter further receives a receive signal and responsively provides a product signal which is then converted to a baseband signal. The demodulator/decoder chip is configured to control the input frequency to the doubler, and further configured to convert the baseband signal to a decoded signal.
摘要翻译：具有用于频率合成的压控振荡器的改进的DBS接收器前端架构。压控振荡器包括具有可调谐谐振频率的振荡电路，其可以在八度以上变化。调谐振荡器驱动储能电路，并将具有该共振频率的信号提供给提供调谐频率的范围扩展器。启用时，扩展器的范围会增加输入频率，而禁用时，只需将输入频率通过。反馈路径向储能电路提供控制电压以调节谐振频率，从而使调谐频率成为参考频率的倍数。扩展器扩展了两个八度的调谐频率范围，而不会损失频率分辨率。广义而言，本发明考虑了一种DBS接收器前端，其包括调谐器芯片和解调器/解码器芯片。调谐器芯片具有倍频器，其在倍频器使能时提供具有输入频率信号的频率的两倍的调谐频率信号，以及当倍频器被禁用时具有等于输入频率信号频率的频率的调谐频率信号。调谐器芯片还具有提供输入频率的调谐振荡器和耦合以接收调谐频率信号的下变频器。下变频器还接收接收信号并且响应地提供产品信号，然后将其转换为基带信号。解调器/解码器芯片被配置为控制到倍频器的输入频率，并且还被配置为将基带信号转换为解码信号。

6. 发明授权

US5870439A Satellite receiver tuner chip having reduced digital noise interference 失效
标题翻译：卫星接收机调谐器芯片具有降低的数字噪声干扰
公开(公告)号：US5870439A
公开(公告)日：1999-02-09
申请号：US878330
申请日：1997-06-18
申请人： Nadav Ben-Efraim , Christopher Keate
发明人： Nadav Ben-Efraim , Christopher Keate
IPC分类号： H04N5/44 , H04B1/10 , H04B1/26 , H04L27/06 , H04L27/22 , H04L27/38 , H04N7/20
CPC分类号： H04L27/066 , H04L27/3863
摘要： A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip having digital interface signals. The tuner chip is configured to receive the digital signals at a reduced peak-to-peak amplitude to reduce the digital interference noise in the tuner chip. The digital signals may also have a limited slew rate to further reduce the digital interference noise. The tuner chip is configured to convert a receive signal to a baseband signal, and the demodulator/decoder chip is configured to convert the baseband signal to a decoded signal.
摘要翻译： DBS接收器前端，其包括调谐器芯片和具有数字接口信号的解调器/解码器芯片。调谐器芯片被配置为以降低的峰 - 峰幅度接收数字信号，以减少调谐器芯片中的数字干扰噪声。数字信号也可能具有有限的转换速率，以进一步减少数字干扰噪声。调谐器芯片被配置为将接收信号转换为基带信号，并且解调器/解码器芯片被配置为将基带信号转换为解码信号。

7. 发明授权

US6091931A Frequency synthesis architecture in a satellite receiver 失效
标题翻译：卫星接收机中的频率综合架构
公开(公告)号：US6091931A
公开(公告)日：2000-07-18
申请号：US878328
申请日：1997-06-18
申请人： Nadav Ben-Efraim , Christopher Keate
发明人： Nadav Ben-Efraim , Christopher Keate
IPC分类号： H04B1/26 , H03D7/16 , H03J1/00 , H03J7/06 , H04B1/16 , H04N7/20
CPC分类号： H03J1/0008 , H03D7/166 , H03J7/065 , H04N7/20
摘要： An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip and the demodulator/decoder chip each include portions of a digital tuning frequency synthesizer. The frequency synthesizer comprises one or more digital counters which are implemented on the demodulator/decoder chip, and an oscillator which is implemented on the tuner chip. This advantageously avoids digital noise interference with the tuner chip while providing a reduced part count. Briefly, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip which cooperate to perform a frequency synthesis function. The tuner chip has a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency, and a downconverter coupled to receive a tuning frequency signal provided by the tuning oscillator. The demodulator/decoder chip has a programmable counter configured to count cycles of the tuning frequency to provide a frequency-divided signal to a phase detector. The phase detector compares the frequency-divided signal to a reference frequency, and is coupled to adjust the resonance frequency of the tank circuit to cause the tuning frequency to have a frequency which is a multiple of the resonance frequency. The demodulator/decoder chip also has a decoder which receives the baseband signal and converts it to a decoded signal.
摘要翻译：具有调谐器芯片和解调器/解码器芯片的改进的DBS接收机前端架构。调谐器芯片和解调器/解码器芯片各自包括数字调谐频率合成器的部分。频率合成器包括在解调器/解码器芯片上实现的一个或多个数字计数器，以及在调谐器芯片上实现的振荡器。这有利地避免了与调谐器芯片的数字噪声干扰，同时提供减少的部件数量。简而言之，本发明涉及一种DBS接收器前端，其包括协调以执行频率合成功能的调谐器芯片和解调器/解码器芯片。调谐器芯片具有耦合到具有可调谐谐振频率的振荡电路的调谐振荡器，以及耦合以接收由调谐振荡器提供的调谐频率信号的下变频器。解调器/解码器芯片具有可编程计数器，其被配置为对调谐频率的周期进行计数以向相位检测器提供分频信号。相位检测器将分频信号与参考频率进行比较，并且耦合以调节振荡电路的谐振频率，以使调谐频率具有作为谐振频率的倍数的频率。解调器/解码器芯片还具有接收基带信号并将其转换为解码信号的解码器。

8. 发明授权

US5835165A Reduction of false locking code words in concatenated decoders 失效
标题翻译：在连接解码器中减少字的伪锁代码
公开(公告)号：US5835165A
公开(公告)日：1998-11-10
申请号：US476434
申请日：1995-06-07
申请人： Christopher Keate , Nadav Ben-Efraim
发明人： Christopher Keate , Nadav Ben-Efraim
IPC分类号： H03M13/29 , H04L1/00 , H04N7/66 , H04N7/64
CPC分类号： H04L1/0057 , H03M13/29 , H04L1/0054 , H04L1/0065 , H04L1/0068 , H04L1/0071
摘要： A concatenated three layer Viterbi, Reed-Solomon/Deinterleaver and Descrambler forward error correction decoder may be utilized in digital video and audio systems, and for direct broadcast satellite applications. The digital signal may be a compressed video and audio signal transmitted from a direct broadcast satellite. Acquisition for three layers of synchronization are required, but once all three layers are in-sync, down stream data synchronization monitoring will suffice so that upstream synchronization monitoring can be disabled thus improving system robustness to noise bursts and false synchronization on false sync bytes generated at the transmission encoder during non-changing data signal conditions.
摘要翻译：连续的三层维特比，里德 - 所罗门/去交织器和解扰器前向纠错解码器可用于数字视频和音频系统以及用于直接广播卫星应用。数字信号可以是从直接广播卫星发送的压缩视频和音频信号。需要采集三层同步，但是一旦所有三个层同步，则下行流数据同步监视就足够了，从而可以禁止上行同步监视，从而提高系统对噪声突发的鲁棒性，并在传输编码器在不变数据信号条件下。

9. 发明授权

US5812927A System and method for correction of I/Q angular error in a satellite receiver 失效
标题翻译：用于校正卫星接收机中I / Q角度误差的系统和方法
公开(公告)号：US5812927A
公开(公告)日：1998-09-22
申请号：US797112
申请日：1997-02-10
申请人： Nadav Ben-Efraim , Christopher Keate
发明人： Nadav Ben-Efraim , Christopher Keate
IPC分类号： H04H40/90 , H04H1/00
CPC分类号： H04H40/90
摘要： A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift, and correcting I/Q angular error and amplitude imbalance. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which digitally performs I/Q angular error correction. The tuner converts the high frequency signal to a baseband signal having an in-phase and a quadrature-phase component. Ideally, the components are separated by ninety degrees, but typically an angular error exists. The demodulator/decoder includes an adaptive equalizer for correcting the angular error. Having the equalizer allows for relaxed tolerances in the tuner.
摘要翻译： DBS接收机前端，将接收的信号直接转换为基带表示，并通过用于跟踪和抵消频率漂移的新技术，以及校正I / Q角度误差和幅度不平衡来维持高性能。 DBS接收机前端包括调谐器和解调器/解码器。调谐器接收高频信号并将其转换为具有频偏误差的基带信号。在一个实施例中，DBS接收器前端包括数字地执行I / Q角度误差校正的解调器/解码器。调谐器将高频信号转换为具有同相和正交相分量的基带信号。理想地，组件分开九十度，但通常存在角度误差。解调器/解码器包括用于校正角度误差的自适应均衡器。使均衡器允许在调谐器中放宽容差。

10. 发明授权

US5844948A System and method for digital tracking and compensation of frequency offset error in a satellite receiver 失效
标题翻译：用于数字跟踪和卫星接收机频偏补偿补偿的系统和方法
公开(公告)号：US5844948A
公开(公告)日：1998-12-01
申请号：US797176
申请日：1997-02-10
申请人： Nadav Ben-Efraim , Christopher R. Keate
发明人： Nadav Ben-Efraim , Christopher R. Keate
IPC分类号： H04H40/90 , H04L27/00 , H04L27/227 , H04L27/06 , H03C3/04 , H04H1/00 , H04L25/06
CPC分类号： H04H40/90 , H04L27/2273 , H04L2027/003 , H04L2027/0057
摘要： A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which receives the baseband signal and produces a compensation signal for canceling the frequency offset error. The demodulator/decoder performs the frequency-offset error compensation digitally. The demodulator/decoder includes an A/D converter which over-samples (samples at a rate of more than two samples per symbol period) the baseband signal and converts it to digital form. The demodulator/decoder also includes a complex multiplier which multiplies the over-sampled digital baseband signal by the compensation signal to produce an offset-error-canceled signal. The complex multiplier is followed by a decimation block which reduces the sample rate of the offset-error-canceled signal to two samples per symbol period. This embodiment has a substantially increased frequency offset tracking range, which allows for the use of relaxed tolerances in the tuner and/or LNB.
摘要翻译： DBS接收器前端，将接收的信号直接转换为基带表示，并通过用于跟踪和抵消频率漂移和I / Q角度误差的新技术来保持高性能。 DBS接收机前端包括调谐器和解调器/解码器。调谐器接收高频信号并将其转换为具有频偏误差的基带信号。在一个实施例中，DBS接收器前端包括解调器/解码器，其接收基带信号并产生用于消除频率偏移误差的补偿信号。解调器/解码器以数字方式执行频偏补偿。解调器/解码器包括A / D转换器，该A / D转换器对基带信号进行过采样（以符号周期多于两个采样的速率采样）并将其转换为数字形式。解调器/解码器还包括复数乘法器，其将过采样数字基带信号乘以补偿信号以产生偏移误差消除信号。复数乘法器之后是抽取块，其将偏移误差消除信号的采样率降低到每符号周期的两个采样。该实施例具有显着增加的频率偏移跟踪范围，其允许在调谐器和/或LNB中使用放宽的公差。

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